SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
83.97 | 95.72 | 83.72 | 89.91 | 75.00 | 88.00 | 98.53 | 56.89 |
T295 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.834571648 | Jul 26 05:45:59 PM PDT 24 | Jul 26 05:46:00 PM PDT 24 | 100264698 ps | ||
T86 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2564908311 | Jul 26 05:45:58 PM PDT 24 | Jul 26 05:46:07 PM PDT 24 | 2329707467 ps | ||
T87 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2315729184 | Jul 26 05:45:51 PM PDT 24 | Jul 26 05:45:53 PM PDT 24 | 109546893 ps | ||
T296 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2750229817 | Jul 26 05:46:07 PM PDT 24 | Jul 26 05:46:13 PM PDT 24 | 4432895924 ps | ||
T297 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3011014785 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:45:53 PM PDT 24 | 209479501 ps | ||
T298 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1299127166 | Jul 26 05:46:02 PM PDT 24 | Jul 26 05:46:04 PM PDT 24 | 118829270 ps | ||
T88 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1915364729 | Jul 26 05:46:08 PM PDT 24 | Jul 26 05:46:17 PM PDT 24 | 2272216059 ps | ||
T299 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1648292962 | Jul 26 05:46:14 PM PDT 24 | Jul 26 05:46:17 PM PDT 24 | 611548646 ps | ||
T300 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1402305452 | Jul 26 05:46:01 PM PDT 24 | Jul 26 05:46:02 PM PDT 24 | 31380705 ps | ||
T301 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2424404797 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:46:25 PM PDT 24 | 40086093548 ps | ||
T91 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3419922303 | Jul 26 05:46:28 PM PDT 24 | Jul 26 05:46:29 PM PDT 24 | 135820720 ps | ||
T92 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.202866374 | Jul 26 05:46:02 PM PDT 24 | Jul 26 05:48:05 PM PDT 24 | 69717135698 ps | ||
T99 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3680806739 | Jul 26 05:45:57 PM PDT 24 | Jul 26 05:45:59 PM PDT 24 | 127646446 ps | ||
T302 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2403287994 | Jul 26 05:45:55 PM PDT 24 | Jul 26 05:45:58 PM PDT 24 | 3448606864 ps | ||
T303 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3664222574 | Jul 26 05:46:23 PM PDT 24 | Jul 26 05:46:25 PM PDT 24 | 1274118056 ps | ||
T304 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3401929032 | Jul 26 05:46:06 PM PDT 24 | Jul 26 05:46:11 PM PDT 24 | 210449303 ps | ||
T305 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1130758229 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:45:48 PM PDT 24 | 167974130 ps | ||
T306 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2050057825 | Jul 26 05:46:24 PM PDT 24 | Jul 26 05:46:28 PM PDT 24 | 172614413 ps | ||
T307 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4084229730 | Jul 26 05:46:04 PM PDT 24 | Jul 26 05:46:07 PM PDT 24 | 91615078 ps | ||
T308 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.496332660 | Jul 26 05:46:04 PM PDT 24 | Jul 26 05:47:32 PM PDT 24 | 50097448183 ps | ||
T309 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1785986297 | Jul 26 05:46:12 PM PDT 24 | Jul 26 05:46:19 PM PDT 24 | 4425507808 ps | ||
T310 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1236724683 | Jul 26 05:45:43 PM PDT 24 | Jul 26 05:45:51 PM PDT 24 | 2298043909 ps | ||
T311 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4032219204 | Jul 26 05:45:44 PM PDT 24 | Jul 26 05:46:08 PM PDT 24 | 74438528253 ps | ||
T312 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4167407809 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:45:53 PM PDT 24 | 1113956570 ps | ||
T313 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1712105153 | Jul 26 05:46:13 PM PDT 24 | Jul 26 05:46:24 PM PDT 24 | 11419294623 ps | ||
T100 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2691178117 | Jul 26 05:45:44 PM PDT 24 | Jul 26 05:46:42 PM PDT 24 | 5652462433 ps | ||
T101 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.268466957 | Jul 26 05:46:21 PM PDT 24 | Jul 26 05:46:24 PM PDT 24 | 322207763 ps | ||
T314 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2144515246 | Jul 26 05:46:10 PM PDT 24 | Jul 26 05:46:25 PM PDT 24 | 14195669737 ps | ||
T315 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4275216593 | Jul 26 05:46:07 PM PDT 24 | Jul 26 05:46:10 PM PDT 24 | 208136717 ps | ||
T316 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.262145708 | Jul 26 05:46:12 PM PDT 24 | Jul 26 05:46:18 PM PDT 24 | 731199135 ps | ||
T109 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3522524057 | Jul 26 05:45:58 PM PDT 24 | Jul 26 05:46:38 PM PDT 24 | 10222411252 ps | ||
T317 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.649212908 | Jul 26 05:46:03 PM PDT 24 | Jul 26 05:46:05 PM PDT 24 | 349836379 ps | ||
T318 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2571668644 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:45:50 PM PDT 24 | 1265621126 ps | ||
T319 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.716315330 | Jul 26 05:46:13 PM PDT 24 | Jul 26 05:46:15 PM PDT 24 | 234916064 ps | ||
T320 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4148484489 | Jul 26 05:45:54 PM PDT 24 | Jul 26 05:45:55 PM PDT 24 | 360477518 ps | ||
T321 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.770069069 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:47:09 PM PDT 24 | 27615860255 ps | ||
T125 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3975412697 | Jul 26 05:46:12 PM PDT 24 | Jul 26 05:46:22 PM PDT 24 | 904769823 ps | ||
T322 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.43580747 | Jul 26 05:46:01 PM PDT 24 | Jul 26 05:46:02 PM PDT 24 | 159368496 ps | ||
T323 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.555644178 | Jul 26 05:46:04 PM PDT 24 | Jul 26 05:46:08 PM PDT 24 | 268750207 ps | ||
T324 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1094974261 | Jul 26 05:46:01 PM PDT 24 | Jul 26 05:46:02 PM PDT 24 | 1092841533 ps | ||
T325 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1735626517 | Jul 26 05:45:51 PM PDT 24 | Jul 26 05:45:54 PM PDT 24 | 1892891432 ps | ||
T102 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.544715418 | Jul 26 05:45:43 PM PDT 24 | Jul 26 05:45:45 PM PDT 24 | 418466471 ps | ||
T93 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2669649335 | Jul 26 05:46:23 PM PDT 24 | Jul 26 05:46:30 PM PDT 24 | 321576605 ps | ||
T326 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3078378228 | Jul 26 05:46:20 PM PDT 24 | Jul 26 05:46:24 PM PDT 24 | 422088330 ps | ||
T327 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1649349177 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:45:48 PM PDT 24 | 90642595 ps | ||
T328 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.726863464 | Jul 26 05:45:59 PM PDT 24 | Jul 26 05:47:57 PM PDT 24 | 32071178284 ps | ||
T329 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.770530529 | Jul 26 05:45:40 PM PDT 24 | Jul 26 05:45:44 PM PDT 24 | 207176506 ps | ||
T330 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1489683799 | Jul 26 05:45:58 PM PDT 24 | Jul 26 05:46:01 PM PDT 24 | 507565427 ps | ||
T331 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2556850002 | Jul 26 05:46:05 PM PDT 24 | Jul 26 05:46:06 PM PDT 24 | 270813097 ps | ||
T103 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.484860215 | Jul 26 05:46:05 PM PDT 24 | Jul 26 05:46:07 PM PDT 24 | 182971933 ps | ||
T332 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.141039619 | Jul 26 05:46:03 PM PDT 24 | Jul 26 05:46:48 PM PDT 24 | 49162369283 ps | ||
T333 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.939490449 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:45:48 PM PDT 24 | 465009763 ps | ||
T159 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2224422034 | Jul 26 05:45:47 PM PDT 24 | Jul 26 05:45:59 PM PDT 24 | 4567507754 ps | ||
T334 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.553554502 | Jul 26 05:45:57 PM PDT 24 | Jul 26 05:45:58 PM PDT 24 | 29916591 ps | ||
T335 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2117410310 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:45:52 PM PDT 24 | 485749323 ps | ||
T104 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2702772987 | Jul 26 05:46:04 PM PDT 24 | Jul 26 05:46:06 PM PDT 24 | 131522260 ps | ||
T158 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4243797828 | Jul 26 05:46:01 PM PDT 24 | Jul 26 05:46:12 PM PDT 24 | 2088234068 ps | ||
T336 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1835520032 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:45:50 PM PDT 24 | 349882040 ps | ||
T337 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1847390338 | Jul 26 05:46:25 PM PDT 24 | Jul 26 05:46:29 PM PDT 24 | 182215493 ps | ||
T112 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2529890741 | Jul 26 05:45:44 PM PDT 24 | Jul 26 05:45:53 PM PDT 24 | 1031522596 ps | ||
T338 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3479421464 | Jul 26 05:46:01 PM PDT 24 | Jul 26 05:46:03 PM PDT 24 | 1058613598 ps | ||
T113 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.429770336 | Jul 26 05:46:01 PM PDT 24 | Jul 26 05:46:08 PM PDT 24 | 253901950 ps | ||
T339 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1617284361 | Jul 26 05:46:00 PM PDT 24 | Jul 26 05:46:13 PM PDT 24 | 13996246505 ps | ||
T340 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2778171982 | Jul 26 05:46:05 PM PDT 24 | Jul 26 05:46:28 PM PDT 24 | 17461092225 ps | ||
T341 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3219585278 | Jul 26 05:46:01 PM PDT 24 | Jul 26 05:46:05 PM PDT 24 | 3208297102 ps | ||
T342 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.973592508 | Jul 26 05:46:08 PM PDT 24 | Jul 26 05:46:14 PM PDT 24 | 236640712 ps | ||
T343 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.911818640 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:46:05 PM PDT 24 | 6641890211 ps | ||
T110 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.43871656 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:46:58 PM PDT 24 | 20403601907 ps | ||
T94 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.274367754 | Jul 26 05:46:05 PM PDT 24 | Jul 26 05:46:13 PM PDT 24 | 2194350666 ps | ||
T344 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2848849108 | Jul 26 05:46:06 PM PDT 24 | Jul 26 05:46:07 PM PDT 24 | 88492541 ps | ||
T345 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3509630893 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:46:03 PM PDT 24 | 4703663189 ps | ||
T346 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3799701605 | Jul 26 05:46:26 PM PDT 24 | Jul 26 05:46:45 PM PDT 24 | 6894398602 ps | ||
T152 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.4185874437 | Jul 26 05:45:55 PM PDT 24 | Jul 26 05:46:04 PM PDT 24 | 3448171573 ps | ||
T347 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2228410867 | Jul 26 05:46:09 PM PDT 24 | Jul 26 05:46:11 PM PDT 24 | 375004501 ps | ||
T95 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1014419628 | Jul 26 05:45:57 PM PDT 24 | Jul 26 05:46:00 PM PDT 24 | 192143125 ps | ||
T348 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2598910591 | Jul 26 05:46:18 PM PDT 24 | Jul 26 05:46:32 PM PDT 24 | 5241965529 ps | ||
T349 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3988034251 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:46:05 PM PDT 24 | 6552962618 ps | ||
T111 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2209611702 | Jul 26 05:46:24 PM PDT 24 | Jul 26 05:46:26 PM PDT 24 | 151259154 ps | ||
T350 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3439630775 | Jul 26 05:45:58 PM PDT 24 | Jul 26 05:46:00 PM PDT 24 | 432208622 ps | ||
T351 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3438076893 | Jul 26 05:46:05 PM PDT 24 | Jul 26 05:46:12 PM PDT 24 | 2722160121 ps | ||
T352 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.353105766 | Jul 26 05:46:01 PM PDT 24 | Jul 26 05:46:08 PM PDT 24 | 2010787243 ps | ||
T353 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1459270939 | Jul 26 05:46:18 PM PDT 24 | Jul 26 05:46:46 PM PDT 24 | 25713817811 ps | ||
T96 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3595781873 | Jul 26 05:45:56 PM PDT 24 | Jul 26 05:46:23 PM PDT 24 | 650552474 ps | ||
T354 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1835163777 | Jul 26 05:45:55 PM PDT 24 | Jul 26 05:45:56 PM PDT 24 | 45269952 ps | ||
T355 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.219809509 | Jul 26 05:46:03 PM PDT 24 | Jul 26 05:46:40 PM PDT 24 | 14887684500 ps | ||
T356 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3790521151 | Jul 26 05:46:14 PM PDT 24 | Jul 26 05:46:15 PM PDT 24 | 147617528 ps | ||
T108 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.765549249 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:45:51 PM PDT 24 | 222247102 ps | ||
T357 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.85311307 | Jul 26 05:45:59 PM PDT 24 | Jul 26 05:46:01 PM PDT 24 | 328733299 ps | ||
T114 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1433765240 | Jul 26 05:46:10 PM PDT 24 | Jul 26 05:46:18 PM PDT 24 | 766097566 ps | ||
T358 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3911544767 | Jul 26 05:46:08 PM PDT 24 | Jul 26 05:46:58 PM PDT 24 | 32431607415 ps | ||
T359 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.52897599 | Jul 26 05:46:08 PM PDT 24 | Jul 26 05:46:35 PM PDT 24 | 2224848362 ps | ||
T360 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.453499595 | Jul 26 05:45:49 PM PDT 24 | Jul 26 05:45:58 PM PDT 24 | 5679895266 ps | ||
T361 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3964424553 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:46:53 PM PDT 24 | 4512718522 ps | ||
T362 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1542492346 | Jul 26 05:45:59 PM PDT 24 | Jul 26 05:46:01 PM PDT 24 | 1035156611 ps | ||
T363 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.106354491 | Jul 26 05:45:57 PM PDT 24 | Jul 26 05:46:01 PM PDT 24 | 230444861 ps | ||
T364 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1738068700 | Jul 26 05:46:15 PM PDT 24 | Jul 26 05:46:16 PM PDT 24 | 219067717 ps | ||
T365 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2601199512 | Jul 26 05:45:56 PM PDT 24 | Jul 26 05:45:58 PM PDT 24 | 122781576 ps | ||
T366 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1401142810 | Jul 26 05:46:00 PM PDT 24 | Jul 26 05:46:03 PM PDT 24 | 204374006 ps | ||
T367 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.674747135 | Jul 26 05:45:58 PM PDT 24 | Jul 26 05:45:59 PM PDT 24 | 663287370 ps | ||
T160 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1706954756 | Jul 26 05:46:27 PM PDT 24 | Jul 26 05:46:51 PM PDT 24 | 4103674611 ps | ||
T368 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1781147600 | Jul 26 05:45:59 PM PDT 24 | Jul 26 05:46:22 PM PDT 24 | 12813516104 ps | ||
T163 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1396670824 | Jul 26 05:46:15 PM PDT 24 | Jul 26 05:46:31 PM PDT 24 | 3164915103 ps | ||
T369 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3695439365 | Jul 26 05:46:01 PM PDT 24 | Jul 26 05:46:03 PM PDT 24 | 207239662 ps | ||
T370 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2766716959 | Jul 26 05:46:07 PM PDT 24 | Jul 26 05:46:09 PM PDT 24 | 216668593 ps | ||
T371 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4208922754 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:46:54 PM PDT 24 | 26969742926 ps | ||
T97 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3714209974 | Jul 26 05:45:57 PM PDT 24 | Jul 26 05:45:59 PM PDT 24 | 63925765 ps | ||
T372 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3983155585 | Jul 26 05:45:51 PM PDT 24 | Jul 26 05:46:18 PM PDT 24 | 16804373397 ps | ||
T373 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.840993911 | Jul 26 05:46:12 PM PDT 24 | Jul 26 05:46:18 PM PDT 24 | 339214251 ps | ||
T374 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1469059166 | Jul 26 05:46:02 PM PDT 24 | Jul 26 05:46:17 PM PDT 24 | 5625681507 ps | ||
T162 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.867396698 | Jul 26 05:46:12 PM PDT 24 | Jul 26 05:46:34 PM PDT 24 | 2066721211 ps | ||
T98 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4159661634 | Jul 26 05:46:19 PM PDT 24 | Jul 26 05:46:27 PM PDT 24 | 533780066 ps | ||
T375 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2745135461 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:46:27 PM PDT 24 | 14801886064 ps | ||
T376 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3523325694 | Jul 26 05:46:25 PM PDT 24 | Jul 26 05:46:31 PM PDT 24 | 562891723 ps | ||
T377 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3110664747 | Jul 26 05:46:25 PM PDT 24 | Jul 26 05:46:29 PM PDT 24 | 192738556 ps | ||
T378 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1063338633 | Jul 26 05:46:23 PM PDT 24 | Jul 26 05:46:26 PM PDT 24 | 1964670749 ps | ||
T379 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2046877211 | Jul 26 05:46:12 PM PDT 24 | Jul 26 05:46:16 PM PDT 24 | 291277066 ps | ||
T380 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2332630523 | Jul 26 05:46:14 PM PDT 24 | Jul 26 05:46:18 PM PDT 24 | 652292010 ps | ||
T381 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3306921788 | Jul 26 05:45:58 PM PDT 24 | Jul 26 05:46:16 PM PDT 24 | 5293051054 ps | ||
T382 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3185100347 | Jul 26 05:46:23 PM PDT 24 | Jul 26 05:46:26 PM PDT 24 | 225971124 ps | ||
T153 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3815122809 | Jul 26 05:46:27 PM PDT 24 | Jul 26 05:46:52 PM PDT 24 | 4208928116 ps | ||
T383 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.4283278481 | Jul 26 05:46:10 PM PDT 24 | Jul 26 05:46:17 PM PDT 24 | 450598178 ps | ||
T384 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1525724375 | Jul 26 05:45:47 PM PDT 24 | Jul 26 05:45:52 PM PDT 24 | 893960108 ps | ||
T385 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1638453134 | Jul 26 05:45:57 PM PDT 24 | Jul 26 05:45:58 PM PDT 24 | 358326954 ps | ||
T386 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3006361585 | Jul 26 05:46:12 PM PDT 24 | Jul 26 05:46:18 PM PDT 24 | 1915062890 ps | ||
T387 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4088121677 | Jul 26 05:46:21 PM PDT 24 | Jul 26 05:48:44 PM PDT 24 | 57021818091 ps | ||
T388 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4200100532 | Jul 26 05:45:56 PM PDT 24 | Jul 26 05:45:57 PM PDT 24 | 103795142 ps | ||
T389 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2243688515 | Jul 26 05:45:47 PM PDT 24 | Jul 26 05:45:56 PM PDT 24 | 2425708551 ps | ||
T390 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1321317790 | Jul 26 05:46:23 PM PDT 24 | Jul 26 05:46:27 PM PDT 24 | 1080284296 ps | ||
T105 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1123487349 | Jul 26 05:45:58 PM PDT 24 | Jul 26 05:46:24 PM PDT 24 | 690477685 ps | ||
T391 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.576133950 | Jul 26 05:46:15 PM PDT 24 | Jul 26 05:46:32 PM PDT 24 | 6018579827 ps | ||
T392 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.185612460 | Jul 26 05:46:00 PM PDT 24 | Jul 26 05:47:09 PM PDT 24 | 7453773198 ps | ||
T393 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.899121412 | Jul 26 05:46:21 PM PDT 24 | Jul 26 05:46:25 PM PDT 24 | 560699430 ps | ||
T106 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2423332607 | Jul 26 05:46:20 PM PDT 24 | Jul 26 05:46:23 PM PDT 24 | 64052052 ps | ||
T394 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1515035460 | Jul 26 05:45:58 PM PDT 24 | Jul 26 05:46:02 PM PDT 24 | 131352918 ps | ||
T395 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2085391375 | Jul 26 05:46:17 PM PDT 24 | Jul 26 05:46:20 PM PDT 24 | 156917725 ps | ||
T154 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3806998878 | Jul 26 05:46:04 PM PDT 24 | Jul 26 05:46:17 PM PDT 24 | 3540553434 ps | ||
T396 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2403587205 | Jul 26 05:46:00 PM PDT 24 | Jul 26 05:46:05 PM PDT 24 | 499214807 ps | ||
T397 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.382505413 | Jul 26 05:45:45 PM PDT 24 | Jul 26 05:46:06 PM PDT 24 | 7310016704 ps | ||
T398 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.493607731 | Jul 26 05:46:04 PM PDT 24 | Jul 26 05:46:07 PM PDT 24 | 311757340 ps | ||
T399 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4138647420 | Jul 26 05:46:21 PM PDT 24 | Jul 26 05:46:22 PM PDT 24 | 285593604 ps | ||
T400 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3996792311 | Jul 26 05:46:20 PM PDT 24 | Jul 26 05:46:21 PM PDT 24 | 1542280695 ps | ||
T401 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2639607060 | Jul 26 05:46:19 PM PDT 24 | Jul 26 05:46:20 PM PDT 24 | 158895302 ps | ||
T402 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2322364433 | Jul 26 05:46:00 PM PDT 24 | Jul 26 05:46:04 PM PDT 24 | 199471358 ps | ||
T164 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2403740549 | Jul 26 05:46:13 PM PDT 24 | Jul 26 05:46:22 PM PDT 24 | 978702173 ps | ||
T403 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2981905030 | Jul 26 05:46:20 PM PDT 24 | Jul 26 05:46:25 PM PDT 24 | 686267083 ps | ||
T404 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2683678656 | Jul 26 05:46:00 PM PDT 24 | Jul 26 05:46:14 PM PDT 24 | 24989294344 ps | ||
T405 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2860466183 | Jul 26 05:46:02 PM PDT 24 | Jul 26 05:46:03 PM PDT 24 | 127752406 ps | ||
T406 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.568136429 | Jul 26 05:46:04 PM PDT 24 | Jul 26 05:46:09 PM PDT 24 | 1633776081 ps | ||
T407 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.55348120 | Jul 26 05:45:49 PM PDT 24 | Jul 26 05:45:51 PM PDT 24 | 256767238 ps | ||
T408 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3711710318 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:45:50 PM PDT 24 | 454024849 ps | ||
T155 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1521975655 | Jul 26 05:46:06 PM PDT 24 | Jul 26 05:46:17 PM PDT 24 | 1811281941 ps | ||
T409 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.531874003 | Jul 26 05:45:58 PM PDT 24 | Jul 26 05:45:59 PM PDT 24 | 65180473 ps | ||
T410 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3105595002 | Jul 26 05:46:03 PM PDT 24 | Jul 26 05:46:05 PM PDT 24 | 5236273250 ps | ||
T411 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4127514859 | Jul 26 05:46:06 PM PDT 24 | Jul 26 05:46:10 PM PDT 24 | 1181047619 ps | ||
T412 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4112384559 | Jul 26 05:46:16 PM PDT 24 | Jul 26 05:46:17 PM PDT 24 | 299369617 ps | ||
T413 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1632352436 | Jul 26 05:45:48 PM PDT 24 | Jul 26 05:45:50 PM PDT 24 | 82504547 ps | ||
T156 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2926438093 | Jul 26 05:46:09 PM PDT 24 | Jul 26 05:46:33 PM PDT 24 | 3698621228 ps | ||
T414 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1207175983 | Jul 26 05:46:30 PM PDT 24 | Jul 26 05:50:18 PM PDT 24 | 86608392332 ps | ||
T415 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.871570758 | Jul 26 05:45:50 PM PDT 24 | Jul 26 05:45:51 PM PDT 24 | 214944376 ps | ||
T157 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4213931420 | Jul 26 05:45:58 PM PDT 24 | Jul 26 05:46:16 PM PDT 24 | 3195852172 ps | ||
T166 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1610181579 | Jul 26 05:46:12 PM PDT 24 | Jul 26 05:46:21 PM PDT 24 | 788394995 ps | ||
T416 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.803384618 | Jul 26 05:46:03 PM PDT 24 | Jul 26 05:46:08 PM PDT 24 | 124826186 ps | ||
T417 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.145562700 | Jul 26 05:46:03 PM PDT 24 | Jul 26 05:46:24 PM PDT 24 | 7736975314 ps | ||
T418 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3576793330 | Jul 26 05:46:05 PM PDT 24 | Jul 26 05:46:45 PM PDT 24 | 25757703967 ps | ||
T419 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1958117557 | Jul 26 05:46:17 PM PDT 24 | Jul 26 05:46:25 PM PDT 24 | 2151545544 ps | ||
T420 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3546992649 | Jul 26 05:46:07 PM PDT 24 | Jul 26 05:46:08 PM PDT 24 | 206408127 ps | ||
T90 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.219397755 | Jul 26 05:45:57 PM PDT 24 | Jul 26 05:46:07 PM PDT 24 | 8938011131 ps | ||
T421 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3447507469 | Jul 26 05:46:13 PM PDT 24 | Jul 26 05:46:15 PM PDT 24 | 87101193 ps | ||
T161 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3917905573 | Jul 26 05:46:15 PM PDT 24 | Jul 26 05:46:25 PM PDT 24 | 1996401492 ps | ||
T422 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1564554807 | Jul 26 05:46:00 PM PDT 24 | Jul 26 05:46:08 PM PDT 24 | 2419260495 ps | ||
T423 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3927908405 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:45:49 PM PDT 24 | 373609025 ps | ||
T424 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.987918062 | Jul 26 05:45:56 PM PDT 24 | Jul 26 05:46:38 PM PDT 24 | 27206347504 ps | ||
T425 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2696649605 | Jul 26 05:46:25 PM PDT 24 | Jul 26 05:46:42 PM PDT 24 | 5555162785 ps | ||
T426 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.763992306 | Jul 26 05:46:13 PM PDT 24 | Jul 26 05:46:18 PM PDT 24 | 312184743 ps | ||
T427 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3992244845 | Jul 26 05:45:47 PM PDT 24 | Jul 26 05:46:01 PM PDT 24 | 4346657286 ps | ||
T428 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3479181734 | Jul 26 05:46:23 PM PDT 24 | Jul 26 05:46:37 PM PDT 24 | 13846108084 ps | ||
T429 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1171776378 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:45:57 PM PDT 24 | 2056888243 ps | ||
T165 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.371748157 | Jul 26 05:45:49 PM PDT 24 | Jul 26 05:46:08 PM PDT 24 | 1873991892 ps | ||
T430 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3124099333 | Jul 26 05:45:59 PM PDT 24 | Jul 26 05:46:00 PM PDT 24 | 294410383 ps | ||
T431 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1880527555 | Jul 26 05:46:26 PM PDT 24 | Jul 26 05:46:34 PM PDT 24 | 4905567298 ps | ||
T432 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4115629012 | Jul 26 05:46:15 PM PDT 24 | Jul 26 05:46:15 PM PDT 24 | 136882530 ps | ||
T433 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3624138940 | Jul 26 05:45:47 PM PDT 24 | Jul 26 05:47:10 PM PDT 24 | 57520212598 ps | ||
T434 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2776426067 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:45:52 PM PDT 24 | 468123686 ps | ||
T435 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4111433829 | Jul 26 05:45:59 PM PDT 24 | Jul 26 05:46:10 PM PDT 24 | 11773968439 ps | ||
T107 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1236910426 | Jul 26 05:46:06 PM PDT 24 | Jul 26 05:46:09 PM PDT 24 | 326970737 ps | ||
T436 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3821262297 | Jul 26 05:45:46 PM PDT 24 | Jul 26 05:45:55 PM PDT 24 | 1117434271 ps | ||
T437 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3056971038 | Jul 26 05:46:19 PM PDT 24 | Jul 26 05:46:26 PM PDT 24 | 179221629 ps | ||
T438 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2888699972 | Jul 26 05:46:01 PM PDT 24 | Jul 26 05:46:04 PM PDT 24 | 125245371 ps | ||
T439 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1277463491 | Jul 26 05:46:19 PM PDT 24 | Jul 26 05:46:21 PM PDT 24 | 194363111 ps | ||
T440 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3614417477 | Jul 26 05:46:16 PM PDT 24 | Jul 26 05:46:18 PM PDT 24 | 453125526 ps | ||
T441 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3460369801 | Jul 26 05:45:49 PM PDT 24 | Jul 26 05:47:10 PM PDT 24 | 16691192038 ps | ||
T442 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1075963496 | Jul 26 05:45:57 PM PDT 24 | Jul 26 05:45:59 PM PDT 24 | 153154877 ps | ||
T443 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.756780464 | Jul 26 05:46:12 PM PDT 24 | Jul 26 05:46:15 PM PDT 24 | 200302156 ps |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.2774197639 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 7325514837 ps |
CPU time | 10.07 seconds |
Started | Jul 26 05:03:03 PM PDT 24 |
Finished | Jul 26 05:03:13 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-cd40c4ce-4bdc-4c5e-affc-a8bc9bbf0b4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774197639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2774197639 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.560326502 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 98072502300 ps |
CPU time | 418.64 seconds |
Started | Jul 26 05:02:32 PM PDT 24 |
Finished | Jul 26 05:09:30 PM PDT 24 |
Peak memory | 229980 kb |
Host | smart-922fec2c-e1f3-4ebb-824b-2ab53d9454bf |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560326502 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.560326502 |
Directory | /workspace/6.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3485001224 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 1542579431 ps |
CPU time | 2.76 seconds |
Started | Jul 26 05:02:34 PM PDT 24 |
Finished | Jul 26 05:02:37 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-530699f5-974d-4b46-86de-4bfbd70b5320 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485001224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3485001224 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.202866374 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 69717135698 ps |
CPU time | 122.79 seconds |
Started | Jul 26 05:46:02 PM PDT 24 |
Finished | Jul 26 05:48:05 PM PDT 24 |
Peak memory | 222548 kb |
Host | smart-36a6bddc-f3d0-4e4f-9b65-d59ba3312815 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202866374 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.202866374 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.4013986645 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 4572108957 ps |
CPU time | 19.89 seconds |
Started | Jul 26 05:46:06 PM PDT 24 |
Finished | Jul 26 05:46:26 PM PDT 24 |
Peak memory | 221708 kb |
Host | smart-a777bb0b-8f14-40c7-a28f-1bbed00073d2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013986645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.4013986645 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.963940889 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 5582883138 ps |
CPU time | 8.74 seconds |
Started | Jul 26 05:02:28 PM PDT 24 |
Finished | Jul 26 05:02:37 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-27f7619c-7f03-40c9-a8c1-4deb647803ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963940889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.963940889 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.3584972776 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 118748404378 ps |
CPU time | 403.54 seconds |
Started | Jul 26 05:02:53 PM PDT 24 |
Finished | Jul 26 05:09:37 PM PDT 24 |
Peak memory | 229892 kb |
Host | smart-83ce97ec-285d-4c4b-a270-d5f8acb1bc83 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584972776 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.3584972776 |
Directory | /workspace/8.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1191555535 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 9340033076 ps |
CPU time | 9.59 seconds |
Started | Jul 26 05:02:57 PM PDT 24 |
Finished | Jul 26 05:03:06 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-cc322fc8-1e31-485a-91b6-ac3ec0648968 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191555535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1191555535 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.498270814 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 65630556 ps |
CPU time | 0.73 seconds |
Started | Jul 26 05:03:04 PM PDT 24 |
Finished | Jul 26 05:03:05 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-b45c9b6a-2d13-4e33-b117-70bfcb06f979 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498270814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.498270814 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.380047925 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 201820695 ps |
CPU time | 0.99 seconds |
Started | Jul 26 05:02:40 PM PDT 24 |
Finished | Jul 26 05:02:41 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-ed9f273e-7725-4a2d-8e50-71800efe5250 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380047925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.380047925 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1566370977 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 1637468633 ps |
CPU time | 4.8 seconds |
Started | Jul 26 05:02:24 PM PDT 24 |
Finished | Jul 26 05:02:29 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-4a650a49-19a0-4e71-9f9e-6bbfae44d1f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566370977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1566370977 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.3394139002 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 211921312930 ps |
CPU time | 1210.16 seconds |
Started | Jul 26 05:02:33 PM PDT 24 |
Finished | Jul 26 05:22:44 PM PDT 24 |
Peak memory | 241160 kb |
Host | smart-fed826a0-b637-43c7-8dc4-5d3abbef0764 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394139002 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.3394139002 |
Directory | /workspace/2.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.2728557942 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 721571342 ps |
CPU time | 3.05 seconds |
Started | Jul 26 05:02:41 PM PDT 24 |
Finished | Jul 26 05:02:45 PM PDT 24 |
Peak memory | 228484 kb |
Host | smart-4056b7d8-b96a-4e13-8cfa-540f2f204fa5 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728557942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2728557942 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.3452124521 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 821230612 ps |
CPU time | 1.29 seconds |
Started | Jul 26 05:02:25 PM PDT 24 |
Finished | Jul 26 05:02:26 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-2d521069-ad6a-4e37-8d06-2b7dbbd2ed37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452124521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3452124521 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.489479300 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 29636784884 ps |
CPU time | 21.25 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:46:10 PM PDT 24 |
Peak memory | 220056 kb |
Host | smart-c5faa7cd-77c5-4742-88ed-00a832af787b |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489479300 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.489479300 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3539526564 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 1682733577 ps |
CPU time | 7.81 seconds |
Started | Jul 26 05:46:24 PM PDT 24 |
Finished | Jul 26 05:46:32 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-a5a13fba-3720-4c12-9cc4-b9c83f50516b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539526564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.3539526564 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.2947262119 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 553454747 ps |
CPU time | 1.03 seconds |
Started | Jul 26 05:02:24 PM PDT 24 |
Finished | Jul 26 05:02:25 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-0c1eb6d9-bc75-450a-87b7-2703c7863975 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947262119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2947262119 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1236910426 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 326970737 ps |
CPU time | 2.34 seconds |
Started | Jul 26 05:46:06 PM PDT 24 |
Finished | Jul 26 05:46:09 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-fb857a12-fea6-45af-8c0c-e329a47bcef1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236910426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1236910426 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.369821026 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 131728648 ps |
CPU time | 0.91 seconds |
Started | Jul 26 05:02:35 PM PDT 24 |
Finished | Jul 26 05:02:36 PM PDT 24 |
Peak memory | 213244 kb |
Host | smart-933e4300-1da3-42ac-9809-bd09a83d2f02 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369821026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.369821026 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3917905573 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 1996401492 ps |
CPU time | 10.08 seconds |
Started | Jul 26 05:46:15 PM PDT 24 |
Finished | Jul 26 05:46:25 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-d4e3dfaf-e430-4e1a-b6d8-b67818892fbf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917905573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3 917905573 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4213931420 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 3195852172 ps |
CPU time | 17.48 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:46:16 PM PDT 24 |
Peak memory | 221084 kb |
Host | smart-f8ad6535-87e2-411b-bde1-7f5ed8079de3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213931420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.4213931420 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.797521123 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 4785060563 ps |
CPU time | 4.12 seconds |
Started | Jul 26 05:02:31 PM PDT 24 |
Finished | Jul 26 05:02:35 PM PDT 24 |
Peak memory | 214692 kb |
Host | smart-d5327226-1d62-45a3-a612-acb740e71651 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797521123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.797521123 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.3006253419 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 8267422999 ps |
CPU time | 9.76 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:03:04 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-a0ef2eb7-09d8-4457-bf01-6b1a14806a0d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006253419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3006253419 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_hartsel_warl.2497776569 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 53374929 ps |
CPU time | 0.76 seconds |
Started | Jul 26 05:02:30 PM PDT 24 |
Finished | Jul 26 05:02:30 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-879e7d98-fd9c-40f4-8402-877f81e6d851 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497776569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2497776569 |
Directory | /workspace/0.rv_dm_hartsel_warl/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.4068141285 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 21056229517 ps |
CPU time | 19.88 seconds |
Started | Jul 26 05:02:45 PM PDT 24 |
Finished | Jul 26 05:03:05 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-95b00b47-7470-468a-ad10-d2ab8fc5bdc7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068141285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.4068141285 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2403740549 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 978702173 ps |
CPU time | 8.56 seconds |
Started | Jul 26 05:46:13 PM PDT 24 |
Finished | Jul 26 05:46:22 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-321e46d2-d57d-470b-8162-fb31d7af5861 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403740549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2 403740549 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.4090784231 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 1575115700 ps |
CPU time | 4.79 seconds |
Started | Jul 26 05:02:43 PM PDT 24 |
Finished | Jul 26 05:02:48 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-f9dc070a-1c92-4fc7-bea4-8f07dc81ce05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090784231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.4090784231 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.4087162206 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 3889628496 ps |
CPU time | 2.85 seconds |
Started | Jul 26 05:02:58 PM PDT 24 |
Finished | Jul 26 05:03:01 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-a6f2e733-fc53-40e6-a8e8-ebd8ef93b2ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087162206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.4087162206 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2547919289 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 9086699885 ps |
CPU time | 4.66 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:32 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-8743dde0-5a04-49c5-bceb-2843470d4037 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547919289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2547919289 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4148484489 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 360477518 ps |
CPU time | 1.13 seconds |
Started | Jul 26 05:45:54 PM PDT 24 |
Finished | Jul 26 05:45:55 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-b6068efe-84f4-43f1-ada1-8711a726bff1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148484489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.4148484489 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2691178117 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 5652462433 ps |
CPU time | 57.79 seconds |
Started | Jul 26 05:45:44 PM PDT 24 |
Finished | Jul 26 05:46:42 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-80ad5f88-e541-4cdb-ab33-f1a659436e5c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691178117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2691178117 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.219397755 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 8938011131 ps |
CPU time | 10.33 seconds |
Started | Jul 26 05:45:57 PM PDT 24 |
Finished | Jul 26 05:46:07 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-7c1f0338-c224-494b-a767-3b7489d36ab8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219397755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr _hw_reset.219397755 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1525892008 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 1744067564 ps |
CPU time | 3.02 seconds |
Started | Jul 26 05:02:35 PM PDT 24 |
Finished | Jul 26 05:02:38 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-8ca101d5-6658-40f0-be8f-e085d929c02a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525892008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1525892008 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2224422034 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 4567507754 ps |
CPU time | 11.46 seconds |
Started | Jul 26 05:45:47 PM PDT 24 |
Finished | Jul 26 05:45:59 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-32c6116f-551a-4a79-8128-b7ff3a569d31 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224422034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2224422034 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.919322448 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 1023212799 ps |
CPU time | 8.66 seconds |
Started | Jul 26 05:46:12 PM PDT 24 |
Finished | Jul 26 05:46:20 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-6e36ce5e-2a81-4cc7-a863-134eb926e5a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919322448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.919322448 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.976177301 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 10774384119 ps |
CPU time | 32.71 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:03:11 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-0e11e152-cce5-4b69-ab02-d757e1e7a4b6 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=976177301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t l_access.976177301 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2423332607 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 64052052 ps |
CPU time | 2.17 seconds |
Started | Jul 26 05:46:20 PM PDT 24 |
Finished | Jul 26 05:46:23 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-ead89179-c3d7-440c-ba5f-8b03e860e92b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423332607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2423332607 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3460369801 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 16691192038 ps |
CPU time | 79.76 seconds |
Started | Jul 26 05:45:49 PM PDT 24 |
Finished | Jul 26 05:47:10 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-7eb45dc9-e93c-4726-a2b0-d49a9ba1c4cd |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460369801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.3460369801 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.43871656 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 20403601907 ps |
CPU time | 69.69 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:46:58 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-90691677-cf99-491c-8e33-4319eded6565 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43871656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.43871656 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3927908405 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 373609025 ps |
CPU time | 2.86 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:45:49 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-785d0ae7-fb65-476f-978e-1fd0641f9fb8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927908405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3927908405 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1525724375 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 893960108 ps |
CPU time | 3.86 seconds |
Started | Jul 26 05:45:47 PM PDT 24 |
Finished | Jul 26 05:45:52 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-a9dad170-ccb1-4442-a1c3-6492542b1132 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525724375 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1525724375 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.765549249 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 222247102 ps |
CPU time | 2.59 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:45:51 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-baed7e48-fb6b-4f56-adb2-e2e4c9f42b6a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765549249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.765549249 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4208922754 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 26969742926 ps |
CPU time | 66.79 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:46:54 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-3f122b83-404a-495c-9825-931e70f07fe3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208922754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.4208922754 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3509630893 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 4703663189 ps |
CPU time | 15.05 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:46:03 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-a83fff48-c9ca-43f2-9228-98f9e17b8e2d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509630893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.3509630893 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.453499595 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 5679895266 ps |
CPU time | 8.59 seconds |
Started | Jul 26 05:45:49 PM PDT 24 |
Finished | Jul 26 05:45:58 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-10c2188d-c67b-4d84-96d1-f16fc340f5a3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453499595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr _hw_reset.453499595 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3988034251 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 6552962618 ps |
CPU time | 15.85 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:46:05 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-199d1661-fc3f-4108-aa05-4e834171c8d2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988034251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3 988034251 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.55348120 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 256767238 ps |
CPU time | 0.99 seconds |
Started | Jul 26 05:45:49 PM PDT 24 |
Finished | Jul 26 05:45:51 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-184f1863-57cb-4921-a0ac-ae76a81ca04d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55348120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_ aliasing.55348120 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.382505413 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 7310016704 ps |
CPU time | 20.53 seconds |
Started | Jul 26 05:45:45 PM PDT 24 |
Finished | Jul 26 05:46:06 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-0ba0f7b1-72cf-478c-978c-9135527030e9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382505413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _bit_bash.382505413 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.871570758 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 214944376 ps |
CPU time | 0.9 seconds |
Started | Jul 26 05:45:50 PM PDT 24 |
Finished | Jul 26 05:45:51 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-3cfc25ce-231d-4034-a053-d1292772f7bc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871570758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.871570758 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1130758229 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 167974130 ps |
CPU time | 0.83 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:45:48 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-5aec3dba-023b-4160-a546-a91e8e0380eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130758229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.1130758229 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3891846476 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 73823430 ps |
CPU time | 0.66 seconds |
Started | Jul 26 05:45:49 PM PDT 24 |
Finished | Jul 26 05:45:50 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-73ef6f09-0dfe-411a-ab0f-3250e9d6137e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891846476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3891846476 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2529890741 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 1031522596 ps |
CPU time | 8.15 seconds |
Started | Jul 26 05:45:44 PM PDT 24 |
Finished | Jul 26 05:45:53 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-9a4c4c0c-6825-4cea-97e1-a391001c9c92 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529890741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.2529890741 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3054299910 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 140989401669 ps |
CPU time | 780.94 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:58:48 PM PDT 24 |
Peak memory | 231804 kb |
Host | smart-6b1518bf-886a-4d52-b4a4-a5aaaf3acaf9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054299910 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3054299910 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2776426067 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 468123686 ps |
CPU time | 5.98 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:45:52 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-f3ba8444-f4a6-4817-b0e0-1fe61149dfda |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776426067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2776426067 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1171776378 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 2056888243 ps |
CPU time | 10.66 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:45:57 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-188dc40c-3758-4dba-ba2e-924dd47c6cec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171776378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1171776378 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3964424553 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 4512718522 ps |
CPU time | 65.62 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:46:53 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-2c02d820-e6f3-4441-83a5-d13ee5d13d58 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964424553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.3964424553 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2315729184 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 109546893 ps |
CPU time | 1.73 seconds |
Started | Jul 26 05:45:51 PM PDT 24 |
Finished | Jul 26 05:45:53 PM PDT 24 |
Peak memory | 213472 kb |
Host | smart-8aef1c0f-b051-4816-8e69-66172e9fe7a0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315729184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2315729184 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.770530529 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 207176506 ps |
CPU time | 3.97 seconds |
Started | Jul 26 05:45:40 PM PDT 24 |
Finished | Jul 26 05:45:44 PM PDT 24 |
Peak memory | 221520 kb |
Host | smart-d065cf3c-8d05-484c-82c4-c9e6f0854542 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770530529 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.770530529 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.544715418 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 418466471 ps |
CPU time | 2.18 seconds |
Started | Jul 26 05:45:43 PM PDT 24 |
Finished | Jul 26 05:45:45 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-d23aa5fd-6794-4671-be9f-728045b54b94 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544715418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.544715418 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2424404797 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 40086093548 ps |
CPU time | 37.57 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:46:25 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-e4bf1bc1-4279-4abb-93b5-ccdec2c87a67 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424404797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.2424404797 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3624138940 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 57520212598 ps |
CPU time | 81.8 seconds |
Started | Jul 26 05:45:47 PM PDT 24 |
Finished | Jul 26 05:47:10 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-d4c835e7-1d0b-4ca8-9834-494dec10f98d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624138940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.3624138940 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.911818640 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 6641890211 ps |
CPU time | 16.57 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:46:05 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-ea0bbbed-80c3-4911-8def-3af4ba4a8461 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911818640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _hw_reset.911818640 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2571668644 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 1265621126 ps |
CPU time | 4.01 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:45:50 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-ff61f921-790a-4e1c-8053-95f26666d8a6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571668644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2 571668644 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3711710318 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 454024849 ps |
CPU time | 1.1 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:45:50 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-9df09b81-6288-4e1a-b4fc-bf4ed1f79a4c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711710318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.3711710318 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.770069069 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 27615860255 ps |
CPU time | 82.86 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:47:09 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-80c5c4a1-c111-48af-acc0-289701ddb96f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770069069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _bit_bash.770069069 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4167407809 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 1113956570 ps |
CPU time | 3.47 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:45:53 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-31d62b7c-e1ad-44d4-a91f-da2f188d4391 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167407809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.4167407809 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1835520032 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 349882040 ps |
CPU time | 1.55 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:45:50 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-4486fe25-3938-4fcd-9868-dfb40713c8b2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835520032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1 835520032 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1632352436 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 82504547 ps |
CPU time | 0.78 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:45:50 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-6047dc56-1152-400d-9648-647202bf1366 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632352436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1632352436 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1649349177 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 90642595 ps |
CPU time | 0.77 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:45:48 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-0ef7f3a2-7df2-4d86-8a9b-9b0c50a19b1e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649349177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1649349177 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3821262297 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 1117434271 ps |
CPU time | 7.73 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:45:55 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-7234ca52-50ca-4163-bc66-705864db8ef7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821262297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3821262297 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4032219204 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 74438528253 ps |
CPU time | 23.94 seconds |
Started | Jul 26 05:45:44 PM PDT 24 |
Finished | Jul 26 05:46:08 PM PDT 24 |
Peak memory | 222760 kb |
Host | smart-54acb0b6-ff77-4968-9102-c61245e118be |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032219204 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.4032219204 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3011014785 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 209479501 ps |
CPU time | 3.69 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:45:53 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-2a500367-8045-4faa-8df0-bea0373baa3d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011014785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3011014785 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.85311307 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 328733299 ps |
CPU time | 2.33 seconds |
Started | Jul 26 05:45:59 PM PDT 24 |
Finished | Jul 26 05:46:01 PM PDT 24 |
Peak memory | 215600 kb |
Host | smart-7d4a15dc-e56a-4a6b-ac00-9c40c02b6556 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85311307 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.85311307 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1469059166 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 5625681507 ps |
CPU time | 14.38 seconds |
Started | Jul 26 05:46:02 PM PDT 24 |
Finished | Jul 26 05:46:17 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-27130e8d-a0f4-49d7-824a-eced1259b2ff |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469059166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.1469059166 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2750229817 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 4432895924 ps |
CPU time | 5.51 seconds |
Started | Jul 26 05:46:07 PM PDT 24 |
Finished | Jul 26 05:46:13 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-b3d1ca0f-613b-41a6-9dd9-57bfd5a379e6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750229817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 2750229817 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1638453134 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 358326954 ps |
CPU time | 1.64 seconds |
Started | Jul 26 05:45:57 PM PDT 24 |
Finished | Jul 26 05:45:58 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-84badcc3-d792-4658-9fc6-3a2217aa34ca |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638453134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 1638453134 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.429770336 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 253901950 ps |
CPU time | 6.68 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:08 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-b5e9401b-446c-4db9-9734-8a1433302028 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429770336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_ csr_outstanding.429770336 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.649212908 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 349836379 ps |
CPU time | 2.24 seconds |
Started | Jul 26 05:46:03 PM PDT 24 |
Finished | Jul 26 05:46:05 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-78480e97-297c-42bf-92db-c65bbb1ec216 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649212908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.649212908 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1521975655 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1811281941 ps |
CPU time | 10.72 seconds |
Started | Jul 26 05:46:06 PM PDT 24 |
Finished | Jul 26 05:46:17 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-fc371305-44fe-4d30-809d-61d8c316cd55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521975655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1 521975655 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4275216593 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 208136717 ps |
CPU time | 2.41 seconds |
Started | Jul 26 05:46:07 PM PDT 24 |
Finished | Jul 26 05:46:10 PM PDT 24 |
Peak memory | 218260 kb |
Host | smart-495daa15-4d97-43cc-b898-c569a3d4e96d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275216593 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.4275216593 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2702772987 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 131522260 ps |
CPU time | 1.61 seconds |
Started | Jul 26 05:46:04 PM PDT 24 |
Finished | Jul 26 05:46:06 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-84c38146-e761-4986-8805-3ff262d753a8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702772987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2702772987 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1348365646 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 14877834960 ps |
CPU time | 29.39 seconds |
Started | Jul 26 05:46:05 PM PDT 24 |
Finished | Jul 26 05:46:35 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-9e7809c5-dce9-4398-a38f-48a1db577590 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348365646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .rv_dm_jtag_dmi_csr_bit_bash.1348365646 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4111433829 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 11773968439 ps |
CPU time | 10.58 seconds |
Started | Jul 26 05:45:59 PM PDT 24 |
Finished | Jul 26 05:46:10 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-a779d1ff-4db7-4585-a114-26d957b297b9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111433829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 4111433829 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2556850002 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 270813097 ps |
CPU time | 0.85 seconds |
Started | Jul 26 05:46:05 PM PDT 24 |
Finished | Jul 26 05:46:06 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-a0f85c7d-f26c-439c-87e7-83616da34e8a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556850002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 2556850002 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.568136429 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 1633776081 ps |
CPU time | 4.53 seconds |
Started | Jul 26 05:46:04 PM PDT 24 |
Finished | Jul 26 05:46:09 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-6e85fe40-8756-4be3-a1a9-5420c2a0b52b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568136429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_ csr_outstanding.568136429 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3450711199 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 231754566 ps |
CPU time | 5.4 seconds |
Started | Jul 26 05:46:04 PM PDT 24 |
Finished | Jul 26 05:46:10 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-32e1723b-f894-4d68-ad89-ad1dd5ddc9ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450711199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3450711199 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3806998878 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 3540553434 ps |
CPU time | 12.53 seconds |
Started | Jul 26 05:46:04 PM PDT 24 |
Finished | Jul 26 05:46:17 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-08d54163-2430-4a1b-842f-024ac307357c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806998878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3 806998878 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1648292962 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 611548646 ps |
CPU time | 2.19 seconds |
Started | Jul 26 05:46:14 PM PDT 24 |
Finished | Jul 26 05:46:17 PM PDT 24 |
Peak memory | 215668 kb |
Host | smart-b3ed5bad-cc46-4569-a64a-3491476cd2db |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648292962 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1648292962 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2085391375 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 156917725 ps |
CPU time | 2.34 seconds |
Started | Jul 26 05:46:17 PM PDT 24 |
Finished | Jul 26 05:46:20 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-8d08f8aa-64ba-4f83-af78-8bd7456a03fc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085391375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2085391375 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1785986297 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 4425507808 ps |
CPU time | 6.97 seconds |
Started | Jul 26 05:46:12 PM PDT 24 |
Finished | Jul 26 05:46:19 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-cbad778e-09c0-4c13-a21e-723d2734f970 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785986297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.1785986297 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.576133950 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 6018579827 ps |
CPU time | 17.28 seconds |
Started | Jul 26 05:46:15 PM PDT 24 |
Finished | Jul 26 05:46:32 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-4272b31b-08fa-44e7-8a23-9288298d585e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576133950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.576133950 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3614417477 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 453125526 ps |
CPU time | 1.34 seconds |
Started | Jul 26 05:46:16 PM PDT 24 |
Finished | Jul 26 05:46:18 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-5a5b300f-26f8-4039-9a90-8e9023a0e0b2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614417477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 3614417477 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2669649335 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 321576605 ps |
CPU time | 6.52 seconds |
Started | Jul 26 05:46:23 PM PDT 24 |
Finished | Jul 26 05:46:30 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-75c4bab7-5535-4ce5-8c97-0860ec22c351 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669649335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.2669649335 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.262145708 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 731199135 ps |
CPU time | 5.09 seconds |
Started | Jul 26 05:46:12 PM PDT 24 |
Finished | Jul 26 05:46:18 PM PDT 24 |
Peak memory | 213484 kb |
Host | smart-a1ca0f8e-365f-4b9c-850f-a9cde25b51c5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262145708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.262145708 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.867396698 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 2066721211 ps |
CPU time | 21.73 seconds |
Started | Jul 26 05:46:12 PM PDT 24 |
Finished | Jul 26 05:46:34 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-20b5467f-d87a-4bad-8d1d-df362d3cc49b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867396698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.867396698 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3078378228 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 422088330 ps |
CPU time | 3.97 seconds |
Started | Jul 26 05:46:20 PM PDT 24 |
Finished | Jul 26 05:46:24 PM PDT 24 |
Peak memory | 219540 kb |
Host | smart-b6602225-560a-429d-ba18-dedf49d07e06 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078378228 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3078378228 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3447507469 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 87101193 ps |
CPU time | 1.73 seconds |
Started | Jul 26 05:46:13 PM PDT 24 |
Finished | Jul 26 05:46:15 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-4508c95f-7bfb-4ba6-ac49-3e12b9034c33 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447507469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3447507469 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1459270939 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 25713817811 ps |
CPU time | 27.14 seconds |
Started | Jul 26 05:46:18 PM PDT 24 |
Finished | Jul 26 05:46:46 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-872b8d33-2575-462f-866e-e527911f6455 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459270939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.1459270939 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1063338633 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 1964670749 ps |
CPU time | 2.55 seconds |
Started | Jul 26 05:46:23 PM PDT 24 |
Finished | Jul 26 05:46:26 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-7854c5d0-3921-4ad4-ac8b-f8dbcb09e185 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063338633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 1063338633 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.716315330 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 234916064 ps |
CPU time | 1.2 seconds |
Started | Jul 26 05:46:13 PM PDT 24 |
Finished | Jul 26 05:46:15 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-72f19d7f-1164-4e0e-b2a0-de2027dc1d4d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716315330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.716315330 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2981905030 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 686267083 ps |
CPU time | 4.59 seconds |
Started | Jul 26 05:46:20 PM PDT 24 |
Finished | Jul 26 05:46:25 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-1b01f06b-d187-4b20-93bc-e184cab9a3ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981905030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.2981905030 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3056971038 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 179221629 ps |
CPU time | 6.3 seconds |
Started | Jul 26 05:46:19 PM PDT 24 |
Finished | Jul 26 05:46:26 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-a1e4c822-527b-443e-92e3-60aa778e2cf9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056971038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3056971038 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1396670824 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 3164915103 ps |
CPU time | 15.88 seconds |
Started | Jul 26 05:46:15 PM PDT 24 |
Finished | Jul 26 05:46:31 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-deb34302-dd57-47df-b88c-94ff24eca8cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396670824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1 396670824 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2050057825 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 172614413 ps |
CPU time | 3.85 seconds |
Started | Jul 26 05:46:24 PM PDT 24 |
Finished | Jul 26 05:46:28 PM PDT 24 |
Peak memory | 221484 kb |
Host | smart-7a86b8c7-8b0d-40fb-9395-7d83bfca4599 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050057825 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2050057825 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1212950049 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 5298007912 ps |
CPU time | 2.66 seconds |
Started | Jul 26 05:46:14 PM PDT 24 |
Finished | Jul 26 05:46:17 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-19266f86-e6e9-47a9-abb6-cd6c8be15999 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212950049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.1212950049 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2598910591 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 5241965529 ps |
CPU time | 13.52 seconds |
Started | Jul 26 05:46:18 PM PDT 24 |
Finished | Jul 26 05:46:32 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-cd474029-0ef0-4c33-896e-daf690b9e3d2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598910591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 2598910591 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4112384559 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 299369617 ps |
CPU time | 0.82 seconds |
Started | Jul 26 05:46:16 PM PDT 24 |
Finished | Jul 26 05:46:17 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-0e5be153-0f1e-4e6a-9699-8230dc5376af |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112384559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 4112384559 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1958117557 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 2151545544 ps |
CPU time | 7.93 seconds |
Started | Jul 26 05:46:17 PM PDT 24 |
Finished | Jul 26 05:46:25 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-6f8df717-ecf4-49ae-81cb-690ba11d2500 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958117557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.1958117557 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1030805077 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 98107430 ps |
CPU time | 2.84 seconds |
Started | Jul 26 05:46:16 PM PDT 24 |
Finished | Jul 26 05:46:19 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-ef0570c3-6aa5-40eb-b360-398a8e033fc1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030805077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1030805077 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3185100347 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 225971124 ps |
CPU time | 2.4 seconds |
Started | Jul 26 05:46:23 PM PDT 24 |
Finished | Jul 26 05:46:26 PM PDT 24 |
Peak memory | 215160 kb |
Host | smart-56b68f1b-48d4-4456-a891-3afe9872f50a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185100347 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3185100347 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1738068700 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 219067717 ps |
CPU time | 1.43 seconds |
Started | Jul 26 05:46:15 PM PDT 24 |
Finished | Jul 26 05:46:16 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-6ee2e137-0ea7-40f7-ac24-f81485ee2461 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738068700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1738068700 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4088121677 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 57021818091 ps |
CPU time | 142.44 seconds |
Started | Jul 26 05:46:21 PM PDT 24 |
Finished | Jul 26 05:48:44 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-dbb7b9c3-7880-41a8-8c83-5517dc31655e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088121677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.4088121677 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4267732857 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 1274026393 ps |
CPU time | 3.69 seconds |
Started | Jul 26 05:46:24 PM PDT 24 |
Finished | Jul 26 05:46:27 PM PDT 24 |
Peak memory | 204340 kb |
Host | smart-d83f4473-3361-4082-abe6-c6870c2d782e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267732857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 4267732857 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3790521151 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 147617528 ps |
CPU time | 0.7 seconds |
Started | Jul 26 05:46:14 PM PDT 24 |
Finished | Jul 26 05:46:15 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-4763f6f4-64f2-4a38-8453-87f3922e8cba |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790521151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 3790521151 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.840993911 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 339214251 ps |
CPU time | 6.49 seconds |
Started | Jul 26 05:46:12 PM PDT 24 |
Finished | Jul 26 05:46:18 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-48ece5d2-5489-4223-892d-85dbe19bb3e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840993911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_ csr_outstanding.840993911 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.899121412 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 560699430 ps |
CPU time | 4.12 seconds |
Started | Jul 26 05:46:21 PM PDT 24 |
Finished | Jul 26 05:46:25 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-b0d0aee1-49a9-44d7-b573-eaa4b9f7fad6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899121412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.899121412 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3975412697 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 904769823 ps |
CPU time | 9.54 seconds |
Started | Jul 26 05:46:12 PM PDT 24 |
Finished | Jul 26 05:46:22 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-c262335d-4f0a-44f8-be08-b2be7ff38400 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975412697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3 975412697 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.763992306 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 312184743 ps |
CPU time | 4.43 seconds |
Started | Jul 26 05:46:13 PM PDT 24 |
Finished | Jul 26 05:46:18 PM PDT 24 |
Peak memory | 220012 kb |
Host | smart-1be1a230-b4ee-4460-9363-0f50f79765ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763992306 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.763992306 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2209611702 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 151259154 ps |
CPU time | 2.44 seconds |
Started | Jul 26 05:46:24 PM PDT 24 |
Finished | Jul 26 05:46:26 PM PDT 24 |
Peak memory | 212524 kb |
Host | smart-40ec2ccf-39e3-4fe4-962f-9fc14bd7ee79 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209611702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2209611702 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1712105153 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 11419294623 ps |
CPU time | 11.12 seconds |
Started | Jul 26 05:46:13 PM PDT 24 |
Finished | Jul 26 05:46:24 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-492005ec-0e70-49b7-893a-401f6a314194 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712105153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.1712105153 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2144515246 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 14195669737 ps |
CPU time | 15.06 seconds |
Started | Jul 26 05:46:10 PM PDT 24 |
Finished | Jul 26 05:46:25 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-415b1b4e-b71f-4a67-aa44-6874eeac8373 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144515246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 2144515246 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4115629012 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 136882530 ps |
CPU time | 0.74 seconds |
Started | Jul 26 05:46:15 PM PDT 24 |
Finished | Jul 26 05:46:15 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-32fea1f7-6c9f-4d69-9bff-4488896f457c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115629012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 4115629012 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1433765240 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 766097566 ps |
CPU time | 7.34 seconds |
Started | Jul 26 05:46:10 PM PDT 24 |
Finished | Jul 26 05:46:18 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-1fca1e63-fac3-419d-882e-d62f3433fad2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433765240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.1433765240 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.4283278481 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 450598178 ps |
CPU time | 6.47 seconds |
Started | Jul 26 05:46:10 PM PDT 24 |
Finished | Jul 26 05:46:17 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-88e8bcaf-bfd1-480a-86a3-120f838308d2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283278481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.4283278481 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1321317790 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 1080284296 ps |
CPU time | 3.6 seconds |
Started | Jul 26 05:46:23 PM PDT 24 |
Finished | Jul 26 05:46:27 PM PDT 24 |
Peak memory | 219224 kb |
Host | smart-eee95a41-52fb-4d59-8908-d61fcadde406 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321317790 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1321317790 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1277463491 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 194363111 ps |
CPU time | 1.5 seconds |
Started | Jul 26 05:46:19 PM PDT 24 |
Finished | Jul 26 05:46:21 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-7f74a502-22d4-44b1-bde6-162aecf2c903 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277463491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1277463491 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3479181734 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 13846108084 ps |
CPU time | 13.02 seconds |
Started | Jul 26 05:46:23 PM PDT 24 |
Finished | Jul 26 05:46:37 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-57cddf8a-bfb4-41e4-bdaa-8f11e6e7a2a0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479181734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.3479181734 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3996792311 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 1542280695 ps |
CPU time | 1.43 seconds |
Started | Jul 26 05:46:20 PM PDT 24 |
Finished | Jul 26 05:46:21 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-6e5801fa-bed8-44de-abfd-bcef96d10b0d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996792311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 3996792311 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4138647420 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 285593604 ps |
CPU time | 0.74 seconds |
Started | Jul 26 05:46:21 PM PDT 24 |
Finished | Jul 26 05:46:22 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-b3e4a189-6885-4ddf-a771-34577b57c2bb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138647420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 4138647420 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4159661634 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 533780066 ps |
CPU time | 7.87 seconds |
Started | Jul 26 05:46:19 PM PDT 24 |
Finished | Jul 26 05:46:27 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-e2d34a91-d9af-4021-9593-0909d227a03f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159661634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.4159661634 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.714878747 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 121879748 ps |
CPU time | 3.48 seconds |
Started | Jul 26 05:46:25 PM PDT 24 |
Finished | Jul 26 05:46:28 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-445afe7a-158e-48ec-977a-1732110976e4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714878747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.714878747 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3110664747 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 192738556 ps |
CPU time | 3.66 seconds |
Started | Jul 26 05:46:25 PM PDT 24 |
Finished | Jul 26 05:46:29 PM PDT 24 |
Peak memory | 221672 kb |
Host | smart-a462dbb9-27d3-433c-96b5-ef6207911c1c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110664747 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3110664747 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.268466957 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 322207763 ps |
CPU time | 2.41 seconds |
Started | Jul 26 05:46:21 PM PDT 24 |
Finished | Jul 26 05:46:24 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-be266ad6-4121-4c74-8d6f-6fab6507c2f9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268466957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.268466957 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1207175983 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 86608392332 ps |
CPU time | 227.01 seconds |
Started | Jul 26 05:46:30 PM PDT 24 |
Finished | Jul 26 05:50:18 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-1c33761b-674a-491a-b2b4-e4e27e32ba59 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207175983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.1207175983 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3664222574 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 1274118056 ps |
CPU time | 1.84 seconds |
Started | Jul 26 05:46:23 PM PDT 24 |
Finished | Jul 26 05:46:25 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-1ec68714-d83c-4a3a-9140-2fbbd77d2baf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664222574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 3664222574 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2639607060 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 158895302 ps |
CPU time | 0.86 seconds |
Started | Jul 26 05:46:19 PM PDT 24 |
Finished | Jul 26 05:46:20 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-9aebd553-1d87-470f-b2f6-a6f5d9e1acb1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639607060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 2639607060 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3523325694 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 562891723 ps |
CPU time | 5.65 seconds |
Started | Jul 26 05:46:25 PM PDT 24 |
Finished | Jul 26 05:46:31 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-064864a2-bb98-47dc-8123-ffb37b610655 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523325694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3523325694 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3815122809 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 4208928116 ps |
CPU time | 24.94 seconds |
Started | Jul 26 05:46:27 PM PDT 24 |
Finished | Jul 26 05:46:52 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-0f245828-56a7-4a87-b987-9670e2015cdc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815122809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3 815122809 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3235200330 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 297394938 ps |
CPU time | 2.31 seconds |
Started | Jul 26 05:46:22 PM PDT 24 |
Finished | Jul 26 05:46:25 PM PDT 24 |
Peak memory | 217668 kb |
Host | smart-64620c1e-23e4-4f00-9d27-2dcae14f4e8d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235200330 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3235200330 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3419922303 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 135820720 ps |
CPU time | 1.43 seconds |
Started | Jul 26 05:46:28 PM PDT 24 |
Finished | Jul 26 05:46:29 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-a52d0805-c3d7-44a1-961b-8bf903bd5cb2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419922303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3419922303 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2696649605 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 5555162785 ps |
CPU time | 16.56 seconds |
Started | Jul 26 05:46:25 PM PDT 24 |
Finished | Jul 26 05:46:42 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-0758718b-3919-4b6b-8c3c-198b27cde725 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696649605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.2696649605 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3799701605 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 6894398602 ps |
CPU time | 18.81 seconds |
Started | Jul 26 05:46:26 PM PDT 24 |
Finished | Jul 26 05:46:45 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-cf526bb9-edc3-4d98-bade-85e6a4a7aaf6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799701605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 3799701605 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.927252773 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 249640979 ps |
CPU time | 0.81 seconds |
Started | Jul 26 05:46:24 PM PDT 24 |
Finished | Jul 26 05:46:25 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-511528a5-1791-4ccc-a946-36030ffbd082 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927252773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.927252773 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1880527555 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 4905567298 ps |
CPU time | 8.27 seconds |
Started | Jul 26 05:46:26 PM PDT 24 |
Finished | Jul 26 05:46:34 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-922e244d-01f0-42f4-8b8b-c8aaba51fd13 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880527555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.1880527555 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1847390338 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 182215493 ps |
CPU time | 3.98 seconds |
Started | Jul 26 05:46:25 PM PDT 24 |
Finished | Jul 26 05:46:29 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-192fe291-cc13-4953-9125-654c38bcef5c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847390338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1847390338 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1706954756 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 4103674611 ps |
CPU time | 23.81 seconds |
Started | Jul 26 05:46:27 PM PDT 24 |
Finished | Jul 26 05:46:51 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-47d0ca1c-a246-4b31-82d1-c262c3c11b63 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706954756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1 706954756 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3595781873 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 650552474 ps |
CPU time | 26.23 seconds |
Started | Jul 26 05:45:56 PM PDT 24 |
Finished | Jul 26 05:46:23 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-2a3e555f-71dc-434a-b934-926dfd663051 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595781873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.3595781873 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.987918062 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 27206347504 ps |
CPU time | 41.88 seconds |
Started | Jul 26 05:45:56 PM PDT 24 |
Finished | Jul 26 05:46:38 PM PDT 24 |
Peak memory | 213540 kb |
Host | smart-493cb5c8-8bd4-437c-88bd-c10e1e51bf14 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987918062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.987918062 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3714209974 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 63925765 ps |
CPU time | 1.56 seconds |
Started | Jul 26 05:45:57 PM PDT 24 |
Finished | Jul 26 05:45:59 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-f12d1a70-b402-4486-93ef-ae137f1e4c2c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714209974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3714209974 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.106354491 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 230444861 ps |
CPU time | 3.71 seconds |
Started | Jul 26 05:45:57 PM PDT 24 |
Finished | Jul 26 05:46:01 PM PDT 24 |
Peak memory | 219116 kb |
Host | smart-b44014d3-e22e-496b-af8e-7f8256b7a60d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106354491 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.106354491 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1401142810 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 204374006 ps |
CPU time | 2.27 seconds |
Started | Jul 26 05:46:00 PM PDT 24 |
Finished | Jul 26 05:46:03 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-3a02bfc1-3386-488e-a8fe-8b5e54990a95 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401142810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1401142810 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3983155585 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 16804373397 ps |
CPU time | 27.1 seconds |
Started | Jul 26 05:45:51 PM PDT 24 |
Finished | Jul 26 05:46:18 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-e15abf3a-78bc-4462-9225-bb9541528c4e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983155585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.3983155585 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3992244845 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 4346657286 ps |
CPU time | 12.97 seconds |
Started | Jul 26 05:45:47 PM PDT 24 |
Finished | Jul 26 05:46:01 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-ed2cd86b-b545-4cb2-8535-4b955478feac |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992244845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.3992244845 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2243688515 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 2425708551 ps |
CPU time | 8.27 seconds |
Started | Jul 26 05:45:47 PM PDT 24 |
Finished | Jul 26 05:45:56 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-845530fb-5486-4940-9c56-8c3725ecb77a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243688515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.2243688515 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2745135461 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 14801886064 ps |
CPU time | 40.66 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:46:27 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-a0c3bc81-6b17-4380-a80a-02605fdd8bf8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745135461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2 745135461 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1735626517 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 1892891432 ps |
CPU time | 2.46 seconds |
Started | Jul 26 05:45:51 PM PDT 24 |
Finished | Jul 26 05:45:54 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-0f7b1eb9-fe4e-49fa-ab4d-82da74cac67a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735626517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.1735626517 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1236724683 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 2298043909 ps |
CPU time | 7.81 seconds |
Started | Jul 26 05:45:43 PM PDT 24 |
Finished | Jul 26 05:45:51 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-c4c25473-cb06-49ab-a4f8-e4c37272202f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236724683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.1236724683 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1382557778 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 934331847 ps |
CPU time | 2.34 seconds |
Started | Jul 26 05:45:47 PM PDT 24 |
Finished | Jul 26 05:45:50 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-c68d90c5-0dd9-45ed-85a1-3af95bab15de |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382557778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.1382557778 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.939490449 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 465009763 ps |
CPU time | 2.03 seconds |
Started | Jul 26 05:45:46 PM PDT 24 |
Finished | Jul 26 05:45:48 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-697c6f84-ee5b-41be-9111-87793cca81fd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939490449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.939490449 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1402305452 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 31380705 ps |
CPU time | 0.75 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:02 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-e8a992b3-c080-435f-8d5b-320397199eed |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402305452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.1402305452 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1835163777 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 45269952 ps |
CPU time | 0.73 seconds |
Started | Jul 26 05:45:55 PM PDT 24 |
Finished | Jul 26 05:45:56 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-897e04d8-8439-4bd2-9b36-85280b72fb13 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835163777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1835163777 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2726538916 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 153148727 ps |
CPU time | 3.64 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:46:02 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-baa09f93-dec1-462c-ba0a-37ce1039db46 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726538916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.2726538916 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2117410310 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 485749323 ps |
CPU time | 3.48 seconds |
Started | Jul 26 05:45:48 PM PDT 24 |
Finished | Jul 26 05:45:52 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-4047e3ae-c7cf-469e-837f-83c5844bd2cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117410310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2117410310 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.371748157 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 1873991892 ps |
CPU time | 18.59 seconds |
Started | Jul 26 05:45:49 PM PDT 24 |
Finished | Jul 26 05:46:08 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-3585e6e4-ba7a-4f21-aad1-42a9f97d204d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371748157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.371748157 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.52897599 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 2224848362 ps |
CPU time | 26.29 seconds |
Started | Jul 26 05:46:08 PM PDT 24 |
Finished | Jul 26 05:46:35 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-7fa3eb11-b999-43fe-b74d-c374e5c03e3d |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52897599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.rv_dm_csr_aliasing.52897599 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3522524057 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 10222411252 ps |
CPU time | 40.63 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:46:38 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-0e2dc747-ced2-4e3a-bda0-78f3aa1f995d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522524057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3522524057 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1014419628 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 192143125 ps |
CPU time | 2.36 seconds |
Started | Jul 26 05:45:57 PM PDT 24 |
Finished | Jul 26 05:46:00 PM PDT 24 |
Peak memory | 213496 kb |
Host | smart-ade4505b-da1f-4711-875e-2b2243585cd5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014419628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1014419628 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.555644178 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 268750207 ps |
CPU time | 4.23 seconds |
Started | Jul 26 05:46:04 PM PDT 24 |
Finished | Jul 26 05:46:08 PM PDT 24 |
Peak memory | 219284 kb |
Host | smart-08a6edce-7f89-4b43-9c45-58244d12fef7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555644178 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.555644178 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2766716959 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 216668593 ps |
CPU time | 1.67 seconds |
Started | Jul 26 05:46:07 PM PDT 24 |
Finished | Jul 26 05:46:09 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-d3cccaa0-7d7b-465e-a144-dba1c0de77b8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766716959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2766716959 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.677670955 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 60751449796 ps |
CPU time | 83.93 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:47:25 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-ea1dbd01-c0a6-46d7-a317-296850ffb28f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677670955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _aliasing.677670955 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3006361585 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 1915062890 ps |
CPU time | 5.69 seconds |
Started | Jul 26 05:46:12 PM PDT 24 |
Finished | Jul 26 05:46:18 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-f0d88b08-c3f1-4b13-9706-b5e68db71785 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006361585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.3006361585 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3105595002 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 5236273250 ps |
CPU time | 2.51 seconds |
Started | Jul 26 05:46:03 PM PDT 24 |
Finished | Jul 26 05:46:05 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-64a2d28d-18bd-4270-bce9-e8783d795081 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105595002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.3105595002 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1826957581 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 290329747 ps |
CPU time | 0.85 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:02 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-544582bc-1a1f-4f19-b5a8-4881b3df3be9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826957581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.1826957581 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2403287994 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 3448606864 ps |
CPU time | 2.73 seconds |
Started | Jul 26 05:45:55 PM PDT 24 |
Finished | Jul 26 05:45:58 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-8af06a0e-c1b9-4379-974e-0d7f4f097ea0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403287994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.2403287994 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1094974261 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 1092841533 ps |
CPU time | 1.45 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:02 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-29ada640-fce5-4849-a5de-823e9e982b70 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094974261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.1094974261 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3546992649 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 206408127 ps |
CPU time | 0.79 seconds |
Started | Jul 26 05:46:07 PM PDT 24 |
Finished | Jul 26 05:46:08 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-c143d680-e65e-4341-89a2-9e95385e9266 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546992649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3 546992649 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.553554502 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 29916591 ps |
CPU time | 0.72 seconds |
Started | Jul 26 05:45:57 PM PDT 24 |
Finished | Jul 26 05:45:58 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-155ccffd-d9c4-484f-96b3-27fd0eae0142 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553554502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part ial_access.553554502 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.834571648 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 100264698 ps |
CPU time | 0.89 seconds |
Started | Jul 26 05:45:59 PM PDT 24 |
Finished | Jul 26 05:46:00 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-ea7d3514-f989-41f4-a6f7-128a578976b3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834571648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.834571648 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2564908311 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 2329707467 ps |
CPU time | 8.03 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:46:07 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-b20c8575-55d7-4cc7-960e-63529b87dd09 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564908311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.2564908311 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.141039619 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 49162369283 ps |
CPU time | 44.82 seconds |
Started | Jul 26 05:46:03 PM PDT 24 |
Finished | Jul 26 05:46:48 PM PDT 24 |
Peak memory | 222760 kb |
Host | smart-f4688e37-1948-4915-88ff-c374846d841e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141039619 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.141039619 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2322364433 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 199471358 ps |
CPU time | 4.49 seconds |
Started | Jul 26 05:46:00 PM PDT 24 |
Finished | Jul 26 05:46:04 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-33952362-22a8-442d-8f56-118863b6f94e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322364433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2322364433 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.4185874437 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 3448171573 ps |
CPU time | 9 seconds |
Started | Jul 26 05:45:55 PM PDT 24 |
Finished | Jul 26 05:46:04 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-bb3ba473-6d35-481a-a6db-dff629fb4d95 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185874437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.4185874437 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1123487349 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 690477685 ps |
CPU time | 25.67 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:46:24 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-c5b08960-610a-4236-a3c5-0865cb7d1fa4 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123487349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.1123487349 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.380783376 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 5122662127 ps |
CPU time | 69.29 seconds |
Started | Jul 26 05:45:59 PM PDT 24 |
Finished | Jul 26 05:47:09 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-f1c20da6-59fa-4dd2-b937-17f7070afeac |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380783376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.380783376 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2601199512 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 122781576 ps |
CPU time | 2.51 seconds |
Started | Jul 26 05:45:56 PM PDT 24 |
Finished | Jul 26 05:45:58 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-e3b54538-2e72-4d00-a0ef-343bb1714ab4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601199512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2601199512 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2403587205 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 499214807 ps |
CPU time | 4.96 seconds |
Started | Jul 26 05:46:00 PM PDT 24 |
Finished | Jul 26 05:46:05 PM PDT 24 |
Peak memory | 221656 kb |
Host | smart-ae1d43a2-8db9-4c90-9931-b6b23d19ca9e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403587205 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2403587205 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3680806739 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 127646446 ps |
CPU time | 2.1 seconds |
Started | Jul 26 05:45:57 PM PDT 24 |
Finished | Jul 26 05:45:59 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-41a9fee0-6515-42aa-bf20-4b1ba4d834b4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680806739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3680806739 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1617284361 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 13996246505 ps |
CPU time | 13.23 seconds |
Started | Jul 26 05:46:00 PM PDT 24 |
Finished | Jul 26 05:46:13 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-6feb42d7-b2bd-4d9f-b8d3-75b4dd1a4ab8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617284361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.1617284361 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2778171982 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 17461092225 ps |
CPU time | 22.67 seconds |
Started | Jul 26 05:46:05 PM PDT 24 |
Finished | Jul 26 05:46:28 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-6b6024b4-232e-42e6-a4b9-a6de7141be19 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778171982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.2778171982 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3438076893 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 2722160121 ps |
CPU time | 7.09 seconds |
Started | Jul 26 05:46:05 PM PDT 24 |
Finished | Jul 26 05:46:12 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-fc1e7e1e-f0a2-4e8b-8053-dd84493fca37 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438076893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3 438076893 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3439630775 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 432208622 ps |
CPU time | 1.85 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:46:00 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-5d33acf1-03bf-48fb-a44a-aa2beb9a1de7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439630775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.3439630775 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.219809509 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 14887684500 ps |
CPU time | 37.01 seconds |
Started | Jul 26 05:46:03 PM PDT 24 |
Finished | Jul 26 05:46:40 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-37b2b17f-8014-497b-b2f8-f2650217b808 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219809509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _bit_bash.219809509 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.674747135 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 663287370 ps |
CPU time | 1.36 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:45:59 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-a89e158d-5899-453c-9588-4e6f79645a5f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674747135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _hw_reset.674747135 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3124099333 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 294410383 ps |
CPU time | 0.83 seconds |
Started | Jul 26 05:45:59 PM PDT 24 |
Finished | Jul 26 05:46:00 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-a57fc02d-0b54-4a09-8710-e6746f73b5b8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124099333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3 124099333 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2848849108 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 88492541 ps |
CPU time | 0.78 seconds |
Started | Jul 26 05:46:06 PM PDT 24 |
Finished | Jul 26 05:46:07 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-21b90f3a-f2aa-4a1d-83c5-feab1bcc2ee1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848849108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.2848849108 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.531874003 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 65180473 ps |
CPU time | 0.74 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:45:59 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-ea241562-38b5-461c-ae4d-5eff3698c470 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531874003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.531874003 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1915364729 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 2272216059 ps |
CPU time | 8.48 seconds |
Started | Jul 26 05:46:08 PM PDT 24 |
Finished | Jul 26 05:46:17 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-1f16c229-1f24-4c34-b344-0a1ca72d7685 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915364729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.1915364729 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.726863464 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 32071178284 ps |
CPU time | 117.38 seconds |
Started | Jul 26 05:45:59 PM PDT 24 |
Finished | Jul 26 05:47:57 PM PDT 24 |
Peak memory | 221688 kb |
Host | smart-f679bcd4-0a19-4ca8-92f6-76722131f2be |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726863464 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.726863464 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2332630523 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 652292010 ps |
CPU time | 3.37 seconds |
Started | Jul 26 05:46:14 PM PDT 24 |
Finished | Jul 26 05:46:18 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-d1e5e8ca-a4a2-4707-8310-dd93c85b7112 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332630523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2332630523 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2926438093 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 3698621228 ps |
CPU time | 24.68 seconds |
Started | Jul 26 05:46:09 PM PDT 24 |
Finished | Jul 26 05:46:33 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-63366be9-a8ae-45ff-b044-a1f257efe97c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926438093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2926438093 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1299127166 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 118829270 ps |
CPU time | 2.28 seconds |
Started | Jul 26 05:46:02 PM PDT 24 |
Finished | Jul 26 05:46:04 PM PDT 24 |
Peak memory | 215116 kb |
Host | smart-b6e95970-d877-4ae7-98cc-bf50d507c2b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299127166 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1299127166 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3776500375 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 173717260 ps |
CPU time | 2.26 seconds |
Started | Jul 26 05:45:57 PM PDT 24 |
Finished | Jul 26 05:45:59 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-676088a9-1f44-490b-ae78-7f60abcca843 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776500375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3776500375 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1781147600 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 12813516104 ps |
CPU time | 22.65 seconds |
Started | Jul 26 05:45:59 PM PDT 24 |
Finished | Jul 26 05:46:22 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-0ceee292-82db-4faf-a909-4a27ea5a5467 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781147600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.1781147600 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1542492346 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 1035156611 ps |
CPU time | 1.17 seconds |
Started | Jul 26 05:45:59 PM PDT 24 |
Finished | Jul 26 05:46:01 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-c94ab946-d074-4d7b-9185-fc3ac2c6e4a3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542492346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1 542492346 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2228410867 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 375004501 ps |
CPU time | 1.59 seconds |
Started | Jul 26 05:46:09 PM PDT 24 |
Finished | Jul 26 05:46:11 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-7be22b51-5e59-44be-85e0-44cf949ac771 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228410867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2 228410867 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1564554807 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 2419260495 ps |
CPU time | 7.78 seconds |
Started | Jul 26 05:46:00 PM PDT 24 |
Finished | Jul 26 05:46:08 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-ea6937bc-c3b8-4cbd-bafd-fdc79aa7cff4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564554807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.1564554807 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.185612460 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 7453773198 ps |
CPU time | 69.05 seconds |
Started | Jul 26 05:46:00 PM PDT 24 |
Finished | Jul 26 05:47:09 PM PDT 24 |
Peak memory | 221344 kb |
Host | smart-c1cdaa79-4fb9-466e-9e8e-1391d5a59eb7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185612460 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.185612460 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3401929032 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 210449303 ps |
CPU time | 4.78 seconds |
Started | Jul 26 05:46:06 PM PDT 24 |
Finished | Jul 26 05:46:11 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-a038c176-bf0b-444e-8ff5-ea652427282d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401929032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3401929032 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.803384618 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 124826186 ps |
CPU time | 4.62 seconds |
Started | Jul 26 05:46:03 PM PDT 24 |
Finished | Jul 26 05:46:08 PM PDT 24 |
Peak memory | 220092 kb |
Host | smart-eed77364-2414-4e2a-844a-7dceb62f6d8b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803384618 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.803384618 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3695439365 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 207239662 ps |
CPU time | 1.75 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:03 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-803049fb-6c7d-4f09-992a-d47613f568f6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695439365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3695439365 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3576793330 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 25757703967 ps |
CPU time | 39.48 seconds |
Started | Jul 26 05:46:05 PM PDT 24 |
Finished | Jul 26 05:46:45 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-24852489-e2a0-4972-b5e6-52780d92f475 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576793330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.3576793330 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.546845234 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 6396747282 ps |
CPU time | 5.16 seconds |
Started | Jul 26 05:45:56 PM PDT 24 |
Finished | Jul 26 05:46:02 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-7bb8a868-1324-408a-b2ac-336b13c03148 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546845234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.546845234 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4200100532 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 103795142 ps |
CPU time | 0.83 seconds |
Started | Jul 26 05:45:56 PM PDT 24 |
Finished | Jul 26 05:45:57 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-499bb81b-83a3-442d-a4b9-a1f10a07fb35 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200100532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4 200100532 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.564538187 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 936889734 ps |
CPU time | 7.74 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:09 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-d8e102cf-b0e6-42d7-a734-4c16bae065b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564538187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c sr_outstanding.564538187 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.973592508 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 236640712 ps |
CPU time | 5.15 seconds |
Started | Jul 26 05:46:08 PM PDT 24 |
Finished | Jul 26 05:46:14 PM PDT 24 |
Peak memory | 213472 kb |
Host | smart-befcac43-379d-4d61-9d2f-34743ec08e04 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973592508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.973592508 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4243797828 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 2088234068 ps |
CPU time | 10.38 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:12 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-cb0a8348-6f5e-4e37-b834-9e7930a45da8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243797828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.4243797828 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1489683799 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 507565427 ps |
CPU time | 2.43 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:46:01 PM PDT 24 |
Peak memory | 215520 kb |
Host | smart-2940bf34-3a08-4746-95f9-7e2a94ffc66c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489683799 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1489683799 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.756780464 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 200302156 ps |
CPU time | 2.37 seconds |
Started | Jul 26 05:46:12 PM PDT 24 |
Finished | Jul 26 05:46:15 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-cdd1d91e-a0c3-4376-a354-b2b7c879b459 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756780464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.756780464 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3911544767 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 32431607415 ps |
CPU time | 49.58 seconds |
Started | Jul 26 05:46:08 PM PDT 24 |
Finished | Jul 26 05:46:58 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-a210382d-1c9f-4202-9551-48f0ded718c1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911544767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.3911544767 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.145562700 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 7736975314 ps |
CPU time | 21.13 seconds |
Started | Jul 26 05:46:03 PM PDT 24 |
Finished | Jul 26 05:46:24 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-89eae48f-d511-4441-bdc9-189f79a471c5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145562700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.145562700 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.43580747 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 159368496 ps |
CPU time | 0.92 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:02 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-8fd75b4b-1877-4b01-a3b7-7885b3be758c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43580747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.43580747 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2046877211 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 291277066 ps |
CPU time | 4.25 seconds |
Started | Jul 26 05:46:12 PM PDT 24 |
Finished | Jul 26 05:46:16 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-b7aa1db0-5ebc-4b68-b5d8-dc8fc970eb24 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046877211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.2046877211 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3659526867 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 74149786746 ps |
CPU time | 66.13 seconds |
Started | Jul 26 05:46:08 PM PDT 24 |
Finished | Jul 26 05:47:15 PM PDT 24 |
Peak memory | 221744 kb |
Host | smart-185d118a-9269-4313-a0a8-dcdfcd026fed |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659526867 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3659526867 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1515035460 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 131352918 ps |
CPU time | 3.41 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:46:02 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-41508890-08a1-4ac8-80d9-434c3d59e91a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515035460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1515035460 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1610181579 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 788394995 ps |
CPU time | 9.2 seconds |
Started | Jul 26 05:46:12 PM PDT 24 |
Finished | Jul 26 05:46:21 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-ab347995-5271-4c60-9c84-a64118c47c9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610181579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1610181579 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1075963496 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 153154877 ps |
CPU time | 2.17 seconds |
Started | Jul 26 05:45:57 PM PDT 24 |
Finished | Jul 26 05:45:59 PM PDT 24 |
Peak memory | 215320 kb |
Host | smart-4ca438cc-c3ca-4aa0-b946-e655fa13b815 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075963496 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1075963496 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.805507852 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 247322851 ps |
CPU time | 1.66 seconds |
Started | Jul 26 05:46:05 PM PDT 24 |
Finished | Jul 26 05:46:07 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-8d0d7574-e7ad-4085-ad04-a3f26059c844 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805507852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.805507852 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2683678656 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 24989294344 ps |
CPU time | 14.63 seconds |
Started | Jul 26 05:46:00 PM PDT 24 |
Finished | Jul 26 05:46:14 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-b1e275b1-11e6-4cf1-b8a5-5dad7c371e21 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683678656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.2683678656 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3219585278 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 3208297102 ps |
CPU time | 4.62 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:05 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-f133cd34-8884-44de-90e3-3cdefb5dfee1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219585278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3 219585278 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3479421464 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 1058613598 ps |
CPU time | 1.71 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:03 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-f764de0b-756b-4b1b-9f1c-24346569c0a7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479421464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3 479421464 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.274367754 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 2194350666 ps |
CPU time | 8.53 seconds |
Started | Jul 26 05:46:05 PM PDT 24 |
Finished | Jul 26 05:46:13 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-e4e2b59c-62cb-4ef8-a91c-7d8e0a7f0f7a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274367754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c sr_outstanding.274367754 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1534174681 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 21368355217 ps |
CPU time | 22.26 seconds |
Started | Jul 26 05:46:09 PM PDT 24 |
Finished | Jul 26 05:46:32 PM PDT 24 |
Peak memory | 221312 kb |
Host | smart-96c9d556-89ce-414d-ac2a-58c771ee7f9b |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534174681 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1534174681 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2888699972 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 125245371 ps |
CPU time | 2.96 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:04 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-ce002cec-c37f-43b2-921e-8760207d300a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888699972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2888699972 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3306921788 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 5293051054 ps |
CPU time | 18.16 seconds |
Started | Jul 26 05:45:58 PM PDT 24 |
Finished | Jul 26 05:46:16 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-11100bba-47cd-42ba-9d82-06b552f26164 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306921788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3306921788 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.493607731 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 311757340 ps |
CPU time | 2.92 seconds |
Started | Jul 26 05:46:04 PM PDT 24 |
Finished | Jul 26 05:46:07 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-732b331e-c085-4952-886d-fa5f1d859849 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493607731 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.493607731 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.484860215 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 182971933 ps |
CPU time | 2.16 seconds |
Started | Jul 26 05:46:05 PM PDT 24 |
Finished | Jul 26 05:46:07 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-4e1342f3-3b11-4d36-ad4a-a5e98e870202 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484860215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.484860215 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.4140567272 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 16148983942 ps |
CPU time | 9.89 seconds |
Started | Jul 26 05:46:09 PM PDT 24 |
Finished | Jul 26 05:46:19 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-56f43e21-b162-4753-8da0-829338e5d7f8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140567272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.4140567272 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.353105766 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 2010787243 ps |
CPU time | 6.55 seconds |
Started | Jul 26 05:46:01 PM PDT 24 |
Finished | Jul 26 05:46:08 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-ea03a3a3-c1de-4990-87d8-ff3eb1c1d5bb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353105766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.353105766 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2860466183 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 127752406 ps |
CPU time | 0.71 seconds |
Started | Jul 26 05:46:02 PM PDT 24 |
Finished | Jul 26 05:46:03 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-8eeb2769-662f-4e54-83e5-bd83de5873cb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860466183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2 860466183 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4127514859 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 1181047619 ps |
CPU time | 4.38 seconds |
Started | Jul 26 05:46:06 PM PDT 24 |
Finished | Jul 26 05:46:10 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-af257608-cbed-4ea3-81f8-273a7647e6b4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127514859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.4127514859 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.496332660 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 50097448183 ps |
CPU time | 86.98 seconds |
Started | Jul 26 05:46:04 PM PDT 24 |
Finished | Jul 26 05:47:32 PM PDT 24 |
Peak memory | 221692 kb |
Host | smart-e4f4fe7f-0695-487e-a23f-dbc88cf14d46 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496332660 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.496332660 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4084229730 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 91615078 ps |
CPU time | 3.16 seconds |
Started | Jul 26 05:46:04 PM PDT 24 |
Finished | Jul 26 05:46:07 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-101249db-e226-44a5-970a-ba222046daa6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084229730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.4084229730 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.1986689448 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 206286215 ps |
CPU time | 0.7 seconds |
Started | Jul 26 05:02:47 PM PDT 24 |
Finished | Jul 26 05:02:47 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-28abb16d-7963-465f-9511-f7cc7cd819e4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986689448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1986689448 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.451957784 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 28678931006 ps |
CPU time | 46.4 seconds |
Started | Jul 26 05:02:40 PM PDT 24 |
Finished | Jul 26 05:03:26 PM PDT 24 |
Peak memory | 213540 kb |
Host | smart-608b6fcf-c117-49ff-bf52-49aba6d2b0c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451957784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.451957784 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.2839993811 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 644077735 ps |
CPU time | 1.3 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:29 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-e06d57b8-850a-4ad2-aaee-2d8ed7a89261 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839993811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2839993811 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2036214839 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 375575755 ps |
CPU time | 1.14 seconds |
Started | Jul 26 05:02:46 PM PDT 24 |
Finished | Jul 26 05:02:47 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-4a74967a-e00b-4d76-922a-27cc6f055e8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036214839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2036214839 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2841735148 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 267530359 ps |
CPU time | 1.18 seconds |
Started | Jul 26 05:02:36 PM PDT 24 |
Finished | Jul 26 05:02:38 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-4b8c9249-4248-471f-bbf9-679a7dd271e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2841735148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2841735148 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.3010681850 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 79129583 ps |
CPU time | 0.89 seconds |
Started | Jul 26 05:02:24 PM PDT 24 |
Finished | Jul 26 05:02:25 PM PDT 24 |
Peak memory | 215096 kb |
Host | smart-1f9f367c-70a4-42a8-9edf-1f1dd8bc0f47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3010681850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3010681850 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2868837904 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 3434001138 ps |
CPU time | 9.98 seconds |
Started | Jul 26 05:02:40 PM PDT 24 |
Finished | Jul 26 05:02:51 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-b0903386-c53b-4d36-93e5-0562c8698a38 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2868837904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.2868837904 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2695871574 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 459863962 ps |
CPU time | 2.03 seconds |
Started | Jul 26 05:02:25 PM PDT 24 |
Finished | Jul 26 05:02:27 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-ef26cb9f-e0fb-48f5-8a00-a54fed5de2c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695871574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2695871574 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.2760627465 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 145765558 ps |
CPU time | 1.02 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:28 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-b8018d5e-85e3-4229-9ad1-f78f9a9d9255 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760627465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2760627465 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2915677701 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 162663581 ps |
CPU time | 0.86 seconds |
Started | Jul 26 05:02:20 PM PDT 24 |
Finished | Jul 26 05:02:21 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-6be57484-1259-4e2f-bee6-4db141e45782 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915677701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2915677701 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.498513319 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 481596832 ps |
CPU time | 1.28 seconds |
Started | Jul 26 05:02:24 PM PDT 24 |
Finished | Jul 26 05:02:26 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-3d07750c-0255-4159-bd34-443b88c5e099 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=498513319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.498513319 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1531327478 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 4662420434 ps |
CPU time | 6.49 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:34 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-d2faa11e-d477-46e3-a1ab-7fd24c705e4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1531327478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1531327478 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2092545485 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 93565614 ps |
CPU time | 1 seconds |
Started | Jul 26 05:02:36 PM PDT 24 |
Finished | Jul 26 05:02:37 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-7995ce40-5900-488b-a103-ee65ffccde2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092545485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2092545485 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.415199417 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 1048748148 ps |
CPU time | 2.17 seconds |
Started | Jul 26 05:02:26 PM PDT 24 |
Finished | Jul 26 05:02:28 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-fea0d169-7800-43f7-a781-665d192d2bf9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415199417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.415199417 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3065830467 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 4188116012 ps |
CPU time | 4.06 seconds |
Started | Jul 26 05:02:23 PM PDT 24 |
Finished | Jul 26 05:02:27 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-e814bb0d-e20b-4723-bdcd-a7bdde37d7a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3065830467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3065830467 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.732149803 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 701795377 ps |
CPU time | 1.64 seconds |
Started | Jul 26 05:02:36 PM PDT 24 |
Finished | Jul 26 05:02:38 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-07517223-0319-49c7-aee2-af18b8a2eba3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=732149803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.732149803 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2575423873 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 549501505 ps |
CPU time | 2.29 seconds |
Started | Jul 26 05:02:26 PM PDT 24 |
Finished | Jul 26 05:02:28 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-053b0ddc-7a84-4267-95c6-fe6b7abdb335 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575423873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2575423873 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.2441020576 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 5562659672 ps |
CPU time | 9.62 seconds |
Started | Jul 26 05:02:24 PM PDT 24 |
Finished | Jul 26 05:02:34 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-631eef45-e7bf-466e-8959-7cc9b22c34bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2441020576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2441020576 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.4097423876 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 894292233 ps |
CPU time | 1.52 seconds |
Started | Jul 26 05:02:30 PM PDT 24 |
Finished | Jul 26 05:02:32 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-3acc5330-8b72-403f-9c30-5ad77c0ca3a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097423876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.4097423876 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.1694735762 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 6032673926 ps |
CPU time | 3.52 seconds |
Started | Jul 26 05:02:28 PM PDT 24 |
Finished | Jul 26 05:02:32 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-772f5be8-fece-450f-ae82-7767ee95c1a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694735762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1694735762 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.436998792 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 146276539 ps |
CPU time | 1.08 seconds |
Started | Jul 26 05:02:30 PM PDT 24 |
Finished | Jul 26 05:02:31 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-ad2624cd-11b8-4785-828f-bea4377c703f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436998792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.436998792 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.2643300040 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 71185348 ps |
CPU time | 0.78 seconds |
Started | Jul 26 05:02:31 PM PDT 24 |
Finished | Jul 26 05:02:32 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-5a3dad71-e745-4eed-8d42-928940ef1274 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643300040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2643300040 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2029536648 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 6921139465 ps |
CPU time | 10.15 seconds |
Started | Jul 26 05:02:48 PM PDT 24 |
Finished | Jul 26 05:02:58 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-97c07f71-da66-4374-9d4c-5de840d449ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029536648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2029536648 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2140860626 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 3203648390 ps |
CPU time | 1.52 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:29 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-5fd733a3-52f8-44da-9de4-9fc798b3246f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140860626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2140860626 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.908353889 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 277294624 ps |
CPU time | 1.36 seconds |
Started | Jul 26 05:02:30 PM PDT 24 |
Finished | Jul 26 05:02:32 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-42532645-73db-4be3-99ee-e93b241de6c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908353889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.908353889 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.548765011 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 381502692 ps |
CPU time | 1.07 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:02:51 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-cdc4b419-0837-4f35-96d1-48191df1ac31 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548765011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.548765011 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.538589206 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 599552452 ps |
CPU time | 1.94 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:29 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-a6f19d8f-5eec-4091-a7c2-454c969024c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=538589206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.538589206 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1712541768 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 514701536 ps |
CPU time | 2.02 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:30 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-feb68958-0a51-4c01-bfd5-a666bf57fa0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1712541768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1712541768 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3727673764 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 315669128 ps |
CPU time | 0.95 seconds |
Started | Jul 26 05:02:25 PM PDT 24 |
Finished | Jul 26 05:02:26 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-b077cac0-09a7-4274-bad4-0bd182a1ef49 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727673764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3727673764 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.352613436 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 151768222 ps |
CPU time | 0.85 seconds |
Started | Jul 26 05:02:29 PM PDT 24 |
Finished | Jul 26 05:02:30 PM PDT 24 |
Peak memory | 215160 kb |
Host | smart-431b01b5-e775-4645-b171-a00e5b0e5bb2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352613436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.352613436 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1455749765 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 2971617830 ps |
CPU time | 1.99 seconds |
Started | Jul 26 05:02:45 PM PDT 24 |
Finished | Jul 26 05:02:47 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-dec9a271-1af4-4bd5-9efb-0d9d7dcd5d70 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1455749765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.1455749765 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.4133763565 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 241129301 ps |
CPU time | 1.02 seconds |
Started | Jul 26 05:02:34 PM PDT 24 |
Finished | Jul 26 05:02:35 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-f3de772f-7222-49d1-9cbc-958b17a864a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133763565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.4133763565 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.4209556233 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 982247893 ps |
CPU time | 1.29 seconds |
Started | Jul 26 05:02:33 PM PDT 24 |
Finished | Jul 26 05:02:34 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-52a242e7-5e10-4419-88c3-489a65f30139 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209556233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.4209556233 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.1917670810 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 210317536 ps |
CPU time | 1.22 seconds |
Started | Jul 26 05:02:28 PM PDT 24 |
Finished | Jul 26 05:02:29 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-86961f56-be67-46f0-b55d-9b7e5d1af51b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1917670810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1917670810 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.658788698 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 130276302 ps |
CPU time | 0.82 seconds |
Started | Jul 26 05:02:43 PM PDT 24 |
Finished | Jul 26 05:02:44 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-17278e39-f871-479b-b5ff-548c69eeac3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=658788698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.658788698 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2858822928 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 400342644 ps |
CPU time | 1.02 seconds |
Started | Jul 26 05:02:25 PM PDT 24 |
Finished | Jul 26 05:02:26 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-e31caafc-dae0-4e23-b1f5-b6374d41f261 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858822928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2858822928 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2342682140 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 1055010987 ps |
CPU time | 2.33 seconds |
Started | Jul 26 05:03:24 PM PDT 24 |
Finished | Jul 26 05:03:27 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-047b9a67-7176-4ace-8ae4-38cb139274fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2342682140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2342682140 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1999664032 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 138875652 ps |
CPU time | 0.88 seconds |
Started | Jul 26 05:02:34 PM PDT 24 |
Finished | Jul 26 05:02:35 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-0baa17b0-867e-49ed-bcdf-89ce0e6a7bcf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999664032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1999664032 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3179831246 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 425915494 ps |
CPU time | 0.89 seconds |
Started | Jul 26 05:02:43 PM PDT 24 |
Finished | Jul 26 05:02:44 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-e83a4da4-0162-4535-ada2-eecc78371005 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3179831246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3179831246 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3256997966 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 713659611 ps |
CPU time | 2.74 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:30 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-5f929956-7451-46de-92dc-df79dba954da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3256997966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3256997966 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.2945780742 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 362669814 ps |
CPU time | 1.31 seconds |
Started | Jul 26 05:02:35 PM PDT 24 |
Finished | Jul 26 05:02:36 PM PDT 24 |
Peak memory | 213172 kb |
Host | smart-20cb773f-dbc3-49fc-9375-f8a5173735c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945780742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2945780742 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1632459604 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 1435771353 ps |
CPU time | 1.45 seconds |
Started | Jul 26 05:02:47 PM PDT 24 |
Finished | Jul 26 05:02:49 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-a1cb0c42-6a1b-4ae8-8ea4-37fedeb04bee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632459604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1632459604 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.1597488710 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 46988559 ps |
CPU time | 0.86 seconds |
Started | Jul 26 05:02:39 PM PDT 24 |
Finished | Jul 26 05:02:40 PM PDT 24 |
Peak memory | 213136 kb |
Host | smart-5d83ff57-9436-4962-b18e-2f8a269b2b62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597488710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1597488710 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2228104573 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 2968476643 ps |
CPU time | 8.26 seconds |
Started | Jul 26 05:02:30 PM PDT 24 |
Finished | Jul 26 05:02:39 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-6019a5b9-1ae5-42db-854e-bf9a85e64627 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228104573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2228104573 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.1651081996 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 2512867755 ps |
CPU time | 6.13 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:34 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-ac8d1f8d-93c6-4d23-b5b1-de5807d42473 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651081996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1651081996 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.2038779015 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 731898040 ps |
CPU time | 2.23 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:29 PM PDT 24 |
Peak memory | 229608 kb |
Host | smart-02fb57cd-fe04-443a-914b-e71a88a1a89e |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038779015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2038779015 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.2780988035 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 2604278494 ps |
CPU time | 4.48 seconds |
Started | Jul 26 05:02:24 PM PDT 24 |
Finished | Jul 26 05:02:29 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-7e8a14c8-a5ec-406c-9f87-2782234da8fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2780988035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2780988035 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.2707096321 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 5291122424 ps |
CPU time | 15.69 seconds |
Started | Jul 26 05:02:43 PM PDT 24 |
Finished | Jul 26 05:02:59 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-8cf0bfe2-f92f-4cb0-8643-9f56b36da016 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707096321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2707096321 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.3403591506 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 39200722 ps |
CPU time | 0.78 seconds |
Started | Jul 26 05:02:32 PM PDT 24 |
Finished | Jul 26 05:02:33 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-97850861-c49a-4c0b-9ec6-1447e5838713 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403591506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3403591506 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.4259247123 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 25625556441 ps |
CPU time | 36.24 seconds |
Started | Jul 26 05:02:55 PM PDT 24 |
Finished | Jul 26 05:03:31 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-c4e6cef8-5747-4d63-9c45-711bb2b877f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259247123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.4259247123 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.425946983 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 2534407121 ps |
CPU time | 2.43 seconds |
Started | Jul 26 05:02:36 PM PDT 24 |
Finished | Jul 26 05:02:39 PM PDT 24 |
Peak memory | 205404 kb |
Host | smart-a1076d14-59c3-45c2-a2e1-c160105e0357 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425946983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.425946983 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2626580343 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 2326996502 ps |
CPU time | 2.22 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:02:41 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-9aa8ca14-8b81-455d-ab8d-80ca2afe55b6 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2626580343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.2626580343 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.3620731838 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 686318129 ps |
CPU time | 1.64 seconds |
Started | Jul 26 05:02:48 PM PDT 24 |
Finished | Jul 26 05:02:50 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-97f83140-a2a8-43f0-aeb7-8b46ba79fc62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620731838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3620731838 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.3706513258 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 8542625961 ps |
CPU time | 7.49 seconds |
Started | Jul 26 05:02:46 PM PDT 24 |
Finished | Jul 26 05:02:53 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-28455802-face-402a-bb44-8798433e16a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706513258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3706513258 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.2384374227 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 70671668 ps |
CPU time | 0.73 seconds |
Started | Jul 26 05:03:09 PM PDT 24 |
Finished | Jul 26 05:03:09 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-1d5b4588-f9e7-4cd1-9517-788d7eb06630 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384374227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2384374227 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1470500544 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 22097549153 ps |
CPU time | 69.02 seconds |
Started | Jul 26 05:02:37 PM PDT 24 |
Finished | Jul 26 05:03:47 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-f8e248f7-b021-4b8f-852a-42bc38a5911f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470500544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1470500544 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3717035793 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 10745245909 ps |
CPU time | 29.35 seconds |
Started | Jul 26 05:02:41 PM PDT 24 |
Finished | Jul 26 05:03:11 PM PDT 24 |
Peak memory | 215228 kb |
Host | smart-80c773bc-0728-4f86-aa46-6df8793d4e99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3717035793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3717035793 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3335135171 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 985280891 ps |
CPU time | 2.93 seconds |
Started | Jul 26 05:02:37 PM PDT 24 |
Finished | Jul 26 05:02:41 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-dd1407a4-031a-4cb3-ba12-0d3a4cafbf90 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3335135171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.3335135171 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.3783873807 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 11264513729 ps |
CPU time | 2.8 seconds |
Started | Jul 26 05:02:46 PM PDT 24 |
Finished | Jul 26 05:02:49 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-99fdfea2-1a21-4bb4-9904-6671956ee935 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783873807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3783873807 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.318950467 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 9705229590 ps |
CPU time | 17.61 seconds |
Started | Jul 26 05:02:39 PM PDT 24 |
Finished | Jul 26 05:02:57 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-5f5b8f1a-4d27-4a23-8102-332779b2b75b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318950467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.318950467 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.126371909 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 139385335 ps |
CPU time | 0.69 seconds |
Started | Jul 26 05:02:40 PM PDT 24 |
Finished | Jul 26 05:02:41 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-12dcf89d-9892-44af-9278-c6b6112fa8e1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126371909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.126371909 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.1539593534 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 32101469711 ps |
CPU time | 29.77 seconds |
Started | Jul 26 05:02:48 PM PDT 24 |
Finished | Jul 26 05:03:17 PM PDT 24 |
Peak memory | 213496 kb |
Host | smart-2e39f2a0-40d2-4442-ac83-433a70c05ed4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539593534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1539593534 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1772383374 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 1040110819 ps |
CPU time | 3.73 seconds |
Started | Jul 26 05:02:41 PM PDT 24 |
Finished | Jul 26 05:02:45 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-f6270a04-c220-40bb-95b3-87bcc29805e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772383374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1772383374 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1716979896 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 9291333418 ps |
CPU time | 13.75 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:02:52 PM PDT 24 |
Peak memory | 213632 kb |
Host | smart-895500db-cc17-4b75-8f4f-32f61593ef50 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1716979896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.1716979896 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.2872065809 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 895166483 ps |
CPU time | 2.02 seconds |
Started | Jul 26 05:02:39 PM PDT 24 |
Finished | Jul 26 05:02:41 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-2a8bf7b3-bfc0-4980-bbc4-23df28594312 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872065809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2872065809 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.3541797659 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 73527467 ps |
CPU time | 0.9 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:02:55 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-78624f2d-5385-41c0-a009-b34d5598e4be |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541797659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3541797659 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1195192636 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1535123116 ps |
CPU time | 2.18 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:02:40 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-8c7ed58e-90b1-4ea6-9927-f25edb0a9b14 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195192636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1195192636 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2937405900 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 961558762 ps |
CPU time | 3.61 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:02:54 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-2b201b8e-32cc-45c2-a980-ab1ae7f781d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2937405900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2937405900 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3231087327 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 2201961214 ps |
CPU time | 7.12 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:02:57 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-219176be-c054-470f-a52e-2fb4a07d7e3d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3231087327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.3231087327 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.4188025795 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 10939338390 ps |
CPU time | 10.27 seconds |
Started | Jul 26 05:02:39 PM PDT 24 |
Finished | Jul 26 05:02:49 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-c757dfd4-9efe-45ad-beb6-4eab905ed99e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188025795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.4188025795 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.1694444833 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 47003448 ps |
CPU time | 0.79 seconds |
Started | Jul 26 05:03:00 PM PDT 24 |
Finished | Jul 26 05:03:01 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-e00091f8-5911-4e48-adb9-442874d075ff |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694444833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1694444833 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1602486187 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 8294716052 ps |
CPU time | 20.7 seconds |
Started | Jul 26 05:02:40 PM PDT 24 |
Finished | Jul 26 05:03:01 PM PDT 24 |
Peak memory | 213620 kb |
Host | smart-28293a5d-8cf5-4757-bed0-0c262dde743d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1602486187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1602486187 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2179913069 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 3245053523 ps |
CPU time | 5.55 seconds |
Started | Jul 26 05:02:37 PM PDT 24 |
Finished | Jul 26 05:02:43 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-368088b2-868d-4be6-aa5d-ecc9bbcbaeb9 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2179913069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.2179913069 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.2852944135 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 11318179909 ps |
CPU time | 31.31 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:03:21 PM PDT 24 |
Peak memory | 213652 kb |
Host | smart-b09cc200-4c4e-44f3-8ab5-29b69d28d98f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852944135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2852944135 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.871679902 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 9032468556 ps |
CPU time | 4.12 seconds |
Started | Jul 26 05:02:51 PM PDT 24 |
Finished | Jul 26 05:02:55 PM PDT 24 |
Peak memory | 213260 kb |
Host | smart-091c6138-1cd2-4f24-844d-48bfe49f894a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871679902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.871679902 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.3359308225 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 37388103 ps |
CPU time | 0.73 seconds |
Started | Jul 26 05:02:41 PM PDT 24 |
Finished | Jul 26 05:02:42 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-aa0f82f6-2306-4d5a-824b-80a1fbb63289 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359308225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3359308225 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1518521574 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 9781420531 ps |
CPU time | 18.76 seconds |
Started | Jul 26 05:02:53 PM PDT 24 |
Finished | Jul 26 05:03:11 PM PDT 24 |
Peak memory | 213540 kb |
Host | smart-1dc254d2-7d05-419b-9021-429286c06ec8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1518521574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1518521574 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3642540423 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 3053828527 ps |
CPU time | 5.04 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:02:44 PM PDT 24 |
Peak memory | 221668 kb |
Host | smart-b17fbcc8-9018-4db5-9944-cd1c779a4e7c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3642540423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3642540423 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4109716144 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 1967574368 ps |
CPU time | 3.81 seconds |
Started | Jul 26 05:02:57 PM PDT 24 |
Finished | Jul 26 05:03:01 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-825cc260-3993-4f9f-b7f2-1872d133e1f9 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4109716144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.4109716144 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.2185284812 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 4231969318 ps |
CPU time | 4.26 seconds |
Started | Jul 26 05:02:39 PM PDT 24 |
Finished | Jul 26 05:02:43 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-9ca88248-e6e4-4be6-8e16-ab1c446cffc8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2185284812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2185284812 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.969957794 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 3686024737 ps |
CPU time | 6.48 seconds |
Started | Jul 26 05:02:37 PM PDT 24 |
Finished | Jul 26 05:02:44 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-f2ac6937-a98f-4a85-8d0a-d13fbce90d5f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969957794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.969957794 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.3375927555 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 66831028 ps |
CPU time | 0.67 seconds |
Started | Jul 26 05:02:55 PM PDT 24 |
Finished | Jul 26 05:02:56 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-2e8ca97a-1517-42e0-9a73-ef89ebae9b4c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375927555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3375927555 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3587783503 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 1594165880 ps |
CPU time | 4.9 seconds |
Started | Jul 26 05:02:48 PM PDT 24 |
Finished | Jul 26 05:02:54 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-fcafd719-9d1d-440d-8ce6-d60dc7a73f5d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3587783503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3587783503 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2160322883 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 5490853509 ps |
CPU time | 9 seconds |
Started | Jul 26 05:02:37 PM PDT 24 |
Finished | Jul 26 05:02:47 PM PDT 24 |
Peak memory | 205448 kb |
Host | smart-cdd643ec-f4d1-444c-b76e-8f917864359b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160322883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2160322883 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.1284627084 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 5229047855 ps |
CPU time | 3.77 seconds |
Started | Jul 26 05:02:39 PM PDT 24 |
Finished | Jul 26 05:02:43 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-40cac460-69b7-4b01-b36c-271c4323686a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284627084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1284627084 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.2476654078 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 3543872917 ps |
CPU time | 3.95 seconds |
Started | Jul 26 05:02:53 PM PDT 24 |
Finished | Jul 26 05:02:57 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-255010fa-f328-4f7c-b5ec-920c72d6e5a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476654078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2476654078 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.3871843827 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 65809079 ps |
CPU time | 0.72 seconds |
Started | Jul 26 05:03:04 PM PDT 24 |
Finished | Jul 26 05:03:04 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-ef718c49-6f36-4166-a602-13ff835c37a1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871843827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3871843827 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3941726638 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 7723529500 ps |
CPU time | 7.31 seconds |
Started | Jul 26 05:02:53 PM PDT 24 |
Finished | Jul 26 05:03:01 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-679634a7-505c-4fdc-886c-34ddc717a218 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941726638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3941726638 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3713983756 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 2173983974 ps |
CPU time | 7.22 seconds |
Started | Jul 26 05:02:37 PM PDT 24 |
Finished | Jul 26 05:02:45 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-d1740e04-66e0-4c22-bd00-31c6fb0d10b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713983756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3713983756 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.518604832 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 10357184920 ps |
CPU time | 28.05 seconds |
Started | Jul 26 05:02:39 PM PDT 24 |
Finished | Jul 26 05:03:08 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-43cbf10c-0da3-43d5-9e15-416c3516be85 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=518604832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t l_access.518604832 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.4243846457 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 4672202124 ps |
CPU time | 7.45 seconds |
Started | Jul 26 05:02:55 PM PDT 24 |
Finished | Jul 26 05:03:02 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-5fa0d2b3-ef51-422f-a626-6eb77b8e1259 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243846457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.4243846457 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.4094693265 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 79820289 ps |
CPU time | 0.77 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:02:55 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-2a31d42a-7a39-4d35-adc7-3f52a2747bb9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094693265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.4094693265 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.795791337 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 3731175156 ps |
CPU time | 6.51 seconds |
Started | Jul 26 05:03:05 PM PDT 24 |
Finished | Jul 26 05:03:11 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-0e3c1d96-f317-485e-a4d6-20e854e8198b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795791337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.795791337 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1949336770 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 1761281979 ps |
CPU time | 2.59 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:02:41 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-6b776416-c02b-4046-b9b9-bea4a9d65f9c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1949336770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.1949336770 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.433328368 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 4342950489 ps |
CPU time | 7.37 seconds |
Started | Jul 26 05:02:55 PM PDT 24 |
Finished | Jul 26 05:03:03 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-61684eb2-92a3-4be4-82a4-7971a505183a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433328368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.433328368 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.2034136685 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 1698881502 ps |
CPU time | 2.17 seconds |
Started | Jul 26 05:02:43 PM PDT 24 |
Finished | Jul 26 05:02:45 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-8a83b662-ce7b-4799-8501-cdceb2e85dd8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034136685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2034136685 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.3152426342 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 61902427 ps |
CPU time | 0.79 seconds |
Started | Jul 26 05:03:02 PM PDT 24 |
Finished | Jul 26 05:03:03 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-99874b61-5df4-4335-b87b-a60c772c3b61 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152426342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3152426342 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.4095578697 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 87268012911 ps |
CPU time | 160.16 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:05:19 PM PDT 24 |
Peak memory | 217188 kb |
Host | smart-7e5d4ee9-8ce8-4c0f-918c-d55b498dff3a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095578697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.4095578697 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.271642519 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 5154909768 ps |
CPU time | 6.83 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:02:57 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-c83f2ff3-6a78-419f-b551-254cf510733e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271642519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.271642519 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.63242347 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 3883198061 ps |
CPU time | 7.22 seconds |
Started | Jul 26 05:02:52 PM PDT 24 |
Finished | Jul 26 05:02:59 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-72b55ab6-b8a5-4b84-b0e4-6a82b2158390 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=63242347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl _access.63242347 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.4256424418 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 2131088442 ps |
CPU time | 3.65 seconds |
Started | Jul 26 05:02:59 PM PDT 24 |
Finished | Jul 26 05:03:03 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-2974434c-d030-4905-a5ee-21a7d01fc71b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4256424418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.4256424418 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.3945661714 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 39935314 ps |
CPU time | 0.71 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:28 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-91f13339-55be-4801-aa1e-1d8d665fcdf5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945661714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3945661714 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.858735843 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 7021921906 ps |
CPU time | 12.07 seconds |
Started | Jul 26 05:02:28 PM PDT 24 |
Finished | Jul 26 05:02:40 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-b2aa5ec8-0c2b-4c68-b46e-ac6227a0bac9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858735843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.858735843 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.313814733 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 2630568974 ps |
CPU time | 3.02 seconds |
Started | Jul 26 05:02:36 PM PDT 24 |
Finished | Jul 26 05:02:39 PM PDT 24 |
Peak memory | 214700 kb |
Host | smart-4e214a31-8dee-4d3b-bdd2-8698ba23f8b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313814733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.313814733 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3464903863 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 2626893429 ps |
CPU time | 8.08 seconds |
Started | Jul 26 05:02:44 PM PDT 24 |
Finished | Jul 26 05:02:52 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-1fa0adf1-9ed8-4e23-aff0-b0252fc2c0ee |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3464903863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.3464903863 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.4019738933 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 69079957 ps |
CPU time | 0.82 seconds |
Started | Jul 26 05:02:48 PM PDT 24 |
Finished | Jul 26 05:02:54 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-20392b75-4c85-4e16-9ae7-577582d0d4c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019738933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.4019738933 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.1711105651 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 1986163988 ps |
CPU time | 2.66 seconds |
Started | Jul 26 05:02:36 PM PDT 24 |
Finished | Jul 26 05:02:39 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-b6fad343-d34b-4897-9be3-1f38d8a502ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711105651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1711105651 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.2782358840 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 669120876 ps |
CPU time | 1.77 seconds |
Started | Jul 26 05:02:37 PM PDT 24 |
Finished | Jul 26 05:02:40 PM PDT 24 |
Peak memory | 229584 kb |
Host | smart-a570dc47-2b41-42fb-95fe-666ffac8f6a4 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782358840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2782358840 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.2190171856 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 34548720 ps |
CPU time | 0.76 seconds |
Started | Jul 26 05:02:39 PM PDT 24 |
Finished | Jul 26 05:02:40 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-792da402-9574-4357-b5b3-8c06b190201b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190171856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2190171856 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.537887521 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 44768785 ps |
CPU time | 0.74 seconds |
Started | Jul 26 05:03:08 PM PDT 24 |
Finished | Jul 26 05:03:09 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-9cb58185-7ed4-4bf5-beea-6c6a918711ee |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537887521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.537887521 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.3382023219 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 3780748370 ps |
CPU time | 6.1 seconds |
Started | Jul 26 05:02:52 PM PDT 24 |
Finished | Jul 26 05:02:58 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-26a94a5a-2ee1-40fd-aa53-b342e05f8e6b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382023219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3382023219 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.129630543 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 155906872 ps |
CPU time | 1.08 seconds |
Started | Jul 26 05:02:41 PM PDT 24 |
Finished | Jul 26 05:02:42 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-b1d86fcf-9b3b-453f-b2b3-1b2235206193 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129630543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.129630543 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.1692772144 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 2578098062 ps |
CPU time | 7.37 seconds |
Started | Jul 26 05:02:42 PM PDT 24 |
Finished | Jul 26 05:02:50 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-8f08bd1a-4933-4e66-bf10-fd75a0cfba43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692772144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1692772144 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.1813694568 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 90297738 ps |
CPU time | 0.71 seconds |
Started | Jul 26 05:02:41 PM PDT 24 |
Finished | Jul 26 05:02:42 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-c8ea41ed-eb19-4baf-b266-fc9d0b75ddc3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813694568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1813694568 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.2531453983 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 2842632456 ps |
CPU time | 9.55 seconds |
Started | Jul 26 05:02:51 PM PDT 24 |
Finished | Jul 26 05:03:01 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-2761994f-55f9-4981-b446-6dfefaf54cb8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531453983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2531453983 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.3481070861 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 110139671 ps |
CPU time | 0.76 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:02:39 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-a905fb36-d179-43ba-978b-8400aac56fac |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481070861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3481070861 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.113949626 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1914133972 ps |
CPU time | 2.22 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:02:41 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-6b4f1e91-55bd-4afc-94a1-15d99eca78c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113949626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.113949626 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.1606649101 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 77921451 ps |
CPU time | 0.71 seconds |
Started | Jul 26 05:03:17 PM PDT 24 |
Finished | Jul 26 05:03:18 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-fcbc1584-a849-4265-96b8-fdea39bb3ea9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606649101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1606649101 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.793774958 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 10638013104 ps |
CPU time | 9.06 seconds |
Started | Jul 26 05:02:58 PM PDT 24 |
Finished | Jul 26 05:03:08 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-df29efb5-5c7b-4891-9936-91a384672b66 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793774958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.793774958 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.2714712977 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 67877204 ps |
CPU time | 0.75 seconds |
Started | Jul 26 05:03:03 PM PDT 24 |
Finished | Jul 26 05:03:03 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-ffc74c7b-b5e2-4eb4-9f76-60ca727625e8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714712977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2714712977 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.4284089913 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 1832032181 ps |
CPU time | 6.15 seconds |
Started | Jul 26 05:02:52 PM PDT 24 |
Finished | Jul 26 05:02:58 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-a2646cb9-d10e-4178-9086-fb4e82b0e1fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284089913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.4284089913 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.168080050 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 70192346 ps |
CPU time | 0.88 seconds |
Started | Jul 26 05:02:53 PM PDT 24 |
Finished | Jul 26 05:02:54 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-34dc7aea-2ae4-4055-b086-9a5ef51be638 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168080050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.168080050 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.2535056887 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 12016123728 ps |
CPU time | 10.57 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:03:05 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-2ce5eb9b-c90b-4aa2-b47f-9bf5948d6a37 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535056887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2535056887 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.3184239425 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 60911606 ps |
CPU time | 0.77 seconds |
Started | Jul 26 05:02:56 PM PDT 24 |
Finished | Jul 26 05:02:57 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-27e30e2d-4642-4fc0-9700-0c7f2b574cb1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184239425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3184239425 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.3734929999 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 1468142421 ps |
CPU time | 4.93 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:02:59 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-1e172324-a77e-45ab-8d80-d48fe783ecc3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734929999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3734929999 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.3039791071 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 76344078 ps |
CPU time | 0.7 seconds |
Started | Jul 26 05:02:58 PM PDT 24 |
Finished | Jul 26 05:02:59 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-c68b419b-7025-4966-a7bc-df8af424cceb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039791071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3039791071 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.3564984435 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 72266620 ps |
CPU time | 0.73 seconds |
Started | Jul 26 05:02:28 PM PDT 24 |
Finished | Jul 26 05:02:29 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-5c9e34fb-f663-4fbd-a66c-6c9705a0823c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564984435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3564984435 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3119556346 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 15779566401 ps |
CPU time | 9.78 seconds |
Started | Jul 26 05:02:32 PM PDT 24 |
Finished | Jul 26 05:02:42 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-49aea430-8784-4551-85fa-53406fd60bec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119556346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3119556346 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.335525064 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 3125308100 ps |
CPU time | 5.68 seconds |
Started | Jul 26 05:02:34 PM PDT 24 |
Finished | Jul 26 05:02:40 PM PDT 24 |
Peak memory | 214208 kb |
Host | smart-06bd5c48-242c-419a-9baf-4afba3c8221e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335525064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.335525064 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3844091068 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 1121638886 ps |
CPU time | 4.22 seconds |
Started | Jul 26 05:02:46 PM PDT 24 |
Finished | Jul 26 05:02:50 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-ac5ca7a0-9937-477b-9e47-dbf5ea09c31d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3844091068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.3844091068 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.4209323549 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 87731639 ps |
CPU time | 0.74 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:02:39 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-60b9af62-c965-4477-8234-82eee7d09f7a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209323549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.4209323549 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.1539064330 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 2846528713 ps |
CPU time | 6.88 seconds |
Started | Jul 26 05:02:51 PM PDT 24 |
Finished | Jul 26 05:02:58 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-25f69206-3ea5-4c1c-b3d2-4e0736897d6c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539064330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1539064330 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.4228395700 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 370119080 ps |
CPU time | 1.17 seconds |
Started | Jul 26 05:02:43 PM PDT 24 |
Finished | Jul 26 05:02:44 PM PDT 24 |
Peak memory | 229212 kb |
Host | smart-75132eb8-9a81-4138-a0cb-9d1d395e8f3b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228395700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.4228395700 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.2849393839 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 8475864636 ps |
CPU time | 5.05 seconds |
Started | Jul 26 05:02:33 PM PDT 24 |
Finished | Jul 26 05:02:38 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-e2d95bed-229f-47c3-bf98-26d64d0846a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849393839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2849393839 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.3989941790 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 103514599868 ps |
CPU time | 429.51 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:10:04 PM PDT 24 |
Peak memory | 227132 kb |
Host | smart-9b2a0e53-f0e5-48cd-8174-189090370235 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989941790 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.3989941790 |
Directory | /workspace/3.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.2331385754 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 84804620 ps |
CPU time | 0.82 seconds |
Started | Jul 26 05:03:12 PM PDT 24 |
Finished | Jul 26 05:03:13 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-a2a6a0bd-be98-46c9-b6f2-3d1ed828b741 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331385754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2331385754 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.2876269627 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 56322373 ps |
CPU time | 0.73 seconds |
Started | Jul 26 05:03:06 PM PDT 24 |
Finished | Jul 26 05:03:07 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-c624ca2c-4c65-4053-9cde-45374ffe4dbc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876269627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2876269627 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.1994656432 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 2242806572 ps |
CPU time | 6.75 seconds |
Started | Jul 26 05:02:55 PM PDT 24 |
Finished | Jul 26 05:03:02 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-0554409d-2a3d-45d1-97cc-8a6c05749cb4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994656432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1994656432 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.3845675109 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 84964969 ps |
CPU time | 0.92 seconds |
Started | Jul 26 05:02:55 PM PDT 24 |
Finished | Jul 26 05:02:56 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-46efb06c-90d9-4da5-ac38-831bd6bac5f1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845675109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3845675109 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.694569817 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 114638790 ps |
CPU time | 0.95 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:03:00 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-32d12d58-f3e3-4f88-89de-cc2ef684cece |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694569817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.694569817 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.489285482 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 2252546177 ps |
CPU time | 3.22 seconds |
Started | Jul 26 05:02:58 PM PDT 24 |
Finished | Jul 26 05:03:01 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-3c970722-66af-4a15-993b-184428537ffc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489285482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.489285482 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.18729743 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 49176132 ps |
CPU time | 0.78 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:02:55 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-37b66709-6776-443d-95f2-6dfe13b61987 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18729743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.18729743 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.592052027 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 51924158 ps |
CPU time | 0.73 seconds |
Started | Jul 26 05:02:52 PM PDT 24 |
Finished | Jul 26 05:02:53 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-abc25b05-f765-4a21-869f-6cb6b6c5f010 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592052027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.592052027 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.4090198652 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 3045167510 ps |
CPU time | 5.45 seconds |
Started | Jul 26 05:02:55 PM PDT 24 |
Finished | Jul 26 05:03:01 PM PDT 24 |
Peak memory | 213400 kb |
Host | smart-17658214-be57-4d47-ba03-5f69339dc073 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090198652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.4090198652 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.2980484429 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 35163797 ps |
CPU time | 0.74 seconds |
Started | Jul 26 05:02:53 PM PDT 24 |
Finished | Jul 26 05:02:54 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-0308732a-c642-474f-9686-a0e1673ca733 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980484429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2980484429 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.2045462934 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 70608449 ps |
CPU time | 0.71 seconds |
Started | Jul 26 05:02:52 PM PDT 24 |
Finished | Jul 26 05:02:53 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-77491450-277a-4e27-b612-649052f1f16a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045462934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2045462934 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.2980954141 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 116098846 ps |
CPU time | 0.82 seconds |
Started | Jul 26 05:02:51 PM PDT 24 |
Finished | Jul 26 05:02:52 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-04828c1c-2d2d-42ca-8b3d-e11aa40d8cf9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980954141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2980954141 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.3504627231 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 5045361919 ps |
CPU time | 8.41 seconds |
Started | Jul 26 05:03:12 PM PDT 24 |
Finished | Jul 26 05:03:21 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-753246c2-f664-4948-bf72-7eac2d757e74 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504627231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3504627231 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.1194555168 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 88040608 ps |
CPU time | 0.74 seconds |
Started | Jul 26 05:02:27 PM PDT 24 |
Finished | Jul 26 05:02:28 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-b491e287-0f5c-4fc6-8f10-c04e45bf8948 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194555168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1194555168 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1421327064 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 60593016594 ps |
CPU time | 27.64 seconds |
Started | Jul 26 05:02:31 PM PDT 24 |
Finished | Jul 26 05:02:59 PM PDT 24 |
Peak memory | 221796 kb |
Host | smart-dd9dd06e-ae32-4a66-84c8-b4f07979cc0e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421327064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1421327064 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1957705787 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 1747461052 ps |
CPU time | 3.37 seconds |
Started | Jul 26 05:02:31 PM PDT 24 |
Finished | Jul 26 05:02:35 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-85f2a920-463f-4386-933c-3c6aaa0d6913 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1957705787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.1957705787 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.1400213160 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 272716629 ps |
CPU time | 1.17 seconds |
Started | Jul 26 05:02:28 PM PDT 24 |
Finished | Jul 26 05:02:29 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-1a159d3d-6206-4d62-ad99-2abba6003879 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400213160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1400213160 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.1093575312 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 749848519 ps |
CPU time | 1.18 seconds |
Started | Jul 26 05:02:30 PM PDT 24 |
Finished | Jul 26 05:02:31 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-db9e0d1e-6c46-4bc7-ba1b-481a8fb15066 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093575312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1093575312 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.2407010488 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 337599924 ps |
CPU time | 1.33 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:02:51 PM PDT 24 |
Peak memory | 229516 kb |
Host | smart-10aaf912-1b27-464f-a273-0ed912c7ff2e |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407010488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2407010488 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.3469764853 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 7973876273 ps |
CPU time | 4.66 seconds |
Started | Jul 26 05:02:29 PM PDT 24 |
Finished | Jul 26 05:02:34 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-7094cb78-0956-4190-9306-a67af5fc6a98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469764853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3469764853 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.192763389 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 821433454075 ps |
CPU time | 1300.77 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:24:31 PM PDT 24 |
Peak memory | 249024 kb |
Host | smart-0b81dd1b-611a-4e26-a792-19e91d6550e5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192763389 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.192763389 |
Directory | /workspace/4.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.773438488 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 173945203 ps |
CPU time | 1.16 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:02:51 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-6df3f80c-73c6-4e30-8c27-4a8187d1fe46 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773438488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.773438488 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.2613832665 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 7438750895 ps |
CPU time | 16.5 seconds |
Started | Jul 26 05:02:58 PM PDT 24 |
Finished | Jul 26 05:03:15 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-e10c4362-e48b-4c49-b0ea-8935d0356b12 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613832665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2613832665 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.559584539 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 41842472 ps |
CPU time | 0.79 seconds |
Started | Jul 26 05:02:57 PM PDT 24 |
Finished | Jul 26 05:02:58 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-08cd747a-0fef-47e2-8245-62d42413bd5f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559584539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.559584539 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.1673677490 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 6518993135 ps |
CPU time | 5.51 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:03:00 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-4e386bf3-2041-4423-9821-015858ddfc52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673677490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1673677490 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.3466670389 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 58481087 ps |
CPU time | 0.82 seconds |
Started | Jul 26 05:03:05 PM PDT 24 |
Finished | Jul 26 05:03:06 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-049973a1-abae-4f65-ac0c-3bb9a3c494bf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466670389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3466670389 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.2666955793 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 68296108 ps |
CPU time | 0.8 seconds |
Started | Jul 26 05:02:55 PM PDT 24 |
Finished | Jul 26 05:02:55 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-69f65066-f6bf-45c9-bfef-a3af7f5f867f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666955793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2666955793 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.3527323963 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 6539294155 ps |
CPU time | 11.17 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:03:01 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-f8230793-0229-412c-bdc3-bf987bf9aacf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527323963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3527323963 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.4029202395 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 162871920 ps |
CPU time | 1.13 seconds |
Started | Jul 26 05:03:16 PM PDT 24 |
Finished | Jul 26 05:03:18 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-31bc92aa-4ce6-4ea9-b968-ef75763191c4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029202395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4029202395 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.2280655991 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 112231709 ps |
CPU time | 0.73 seconds |
Started | Jul 26 05:02:55 PM PDT 24 |
Finished | Jul 26 05:02:56 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-cf4c13a2-53eb-46e1-8efc-16ef9667907f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280655991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2280655991 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.3912744070 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 2760727228 ps |
CPU time | 4.04 seconds |
Started | Jul 26 05:02:58 PM PDT 24 |
Finished | Jul 26 05:03:02 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-197a327a-541f-4089-8f7d-55c45d4b347a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912744070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3912744070 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.1939634341 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 93314491 ps |
CPU time | 0.9 seconds |
Started | Jul 26 05:03:02 PM PDT 24 |
Finished | Jul 26 05:03:03 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-c401bf9d-55b3-48a2-a864-7891a2eb5842 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939634341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1939634341 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.3106766723 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 5050248391 ps |
CPU time | 14.86 seconds |
Started | Jul 26 05:03:06 PM PDT 24 |
Finished | Jul 26 05:03:21 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-bab5ed10-57d0-42b6-92ee-f019d8bfbf0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106766723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3106766723 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.3020824521 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 105645347 ps |
CPU time | 0.75 seconds |
Started | Jul 26 05:03:16 PM PDT 24 |
Finished | Jul 26 05:03:17 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-867d6b08-e17b-4d21-bd3d-bdb81f9cf2cb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020824521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3020824521 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.2987997032 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 51761610 ps |
CPU time | 0.81 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:02:55 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-985746f8-e30c-43f7-94ab-75300b806231 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987997032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2987997032 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.1994573565 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 39702164 ps |
CPU time | 0.77 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:02:55 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-9da36488-fdbc-4bca-8df6-34cd3093a70c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994573565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1994573565 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.2119253417 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 10311492071 ps |
CPU time | 14.87 seconds |
Started | Jul 26 05:02:49 PM PDT 24 |
Finished | Jul 26 05:03:04 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-b7ad375e-c37b-4e12-aa7e-9b53611d9168 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119253417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2119253417 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.3056665822 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 63467736 ps |
CPU time | 0.76 seconds |
Started | Jul 26 05:02:37 PM PDT 24 |
Finished | Jul 26 05:02:38 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-1bcd40a6-ab70-4ec1-9085-14bff2d8b778 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056665822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3056665822 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3018050256 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 901265323 ps |
CPU time | 2.24 seconds |
Started | Jul 26 05:02:35 PM PDT 24 |
Finished | Jul 26 05:02:37 PM PDT 24 |
Peak memory | 205404 kb |
Host | smart-42f0339a-7e7a-4545-8775-0501bbdca9f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018050256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3018050256 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1734430382 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 11854722992 ps |
CPU time | 14.77 seconds |
Started | Jul 26 05:02:31 PM PDT 24 |
Finished | Jul 26 05:02:51 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-e8352c13-0431-43f9-acf7-5fb312b1094e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1734430382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.1734430382 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.3572045695 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 1252113512 ps |
CPU time | 3.05 seconds |
Started | Jul 26 05:02:44 PM PDT 24 |
Finished | Jul 26 05:02:47 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-2d045042-0fac-4811-9c27-b70a09e158dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3572045695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3572045695 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.3142429242 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 15729943086 ps |
CPU time | 114.19 seconds |
Started | Jul 26 05:02:31 PM PDT 24 |
Finished | Jul 26 05:04:26 PM PDT 24 |
Peak memory | 220248 kb |
Host | smart-ee55a374-dbbf-41c0-8cf5-96cd2f5a1cb4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142429242 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.3142429242 |
Directory | /workspace/5.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.1425508896 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 103104684 ps |
CPU time | 0.78 seconds |
Started | Jul 26 05:02:38 PM PDT 24 |
Finished | Jul 26 05:02:39 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-7ca72501-c75c-4334-bfe2-ccf9a12da965 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425508896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1425508896 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.4161488127 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 2525491300 ps |
CPU time | 2.03 seconds |
Started | Jul 26 05:02:30 PM PDT 24 |
Finished | Jul 26 05:02:32 PM PDT 24 |
Peak memory | 214908 kb |
Host | smart-18e6395e-d482-445d-a6f7-366902c55693 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161488127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.4161488127 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.742166040 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 2755628633 ps |
CPU time | 8.6 seconds |
Started | Jul 26 05:02:32 PM PDT 24 |
Finished | Jul 26 05:02:41 PM PDT 24 |
Peak memory | 205460 kb |
Host | smart-13a40c75-2899-497e-830d-f4ce766eb318 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=742166040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl _access.742166040 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.4211033837 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 1090381178 ps |
CPU time | 1.48 seconds |
Started | Jul 26 05:02:41 PM PDT 24 |
Finished | Jul 26 05:02:43 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-de7ee4c4-9dcf-4ae4-a762-b66321237af7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211033837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.4211033837 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.1262317678 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 11483455000 ps |
CPU time | 17.57 seconds |
Started | Jul 26 05:02:35 PM PDT 24 |
Finished | Jul 26 05:02:52 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-be6e54c3-fd25-4931-b9c2-bf64ab9afe29 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262317678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1262317678 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.3773532246 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 83549910 ps |
CPU time | 0.76 seconds |
Started | Jul 26 05:02:55 PM PDT 24 |
Finished | Jul 26 05:02:56 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-9c88b69f-ec09-43ea-bc67-e19323decbb1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773532246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3773532246 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1345936654 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 48630965439 ps |
CPU time | 40.87 seconds |
Started | Jul 26 05:02:35 PM PDT 24 |
Finished | Jul 26 05:03:16 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-11f736ad-8c5e-411a-a4b0-bb28d6493ff4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345936654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1345936654 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.308474107 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 3379138878 ps |
CPU time | 3.35 seconds |
Started | Jul 26 05:02:35 PM PDT 24 |
Finished | Jul 26 05:02:38 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-02604fe5-7d5c-4426-a02c-79d3d1bd8ae1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308474107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.308474107 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4184110085 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 7222800918 ps |
CPU time | 20.9 seconds |
Started | Jul 26 05:02:44 PM PDT 24 |
Finished | Jul 26 05:03:05 PM PDT 24 |
Peak memory | 213648 kb |
Host | smart-21e4fb79-db71-4733-8de6-799ebeda2785 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4184110085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.4184110085 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.967864139 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 2403028306 ps |
CPU time | 7.66 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:02:58 PM PDT 24 |
Peak memory | 205368 kb |
Host | smart-66ceffd4-6554-45a8-b7e1-432b6421f46d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=967864139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.967864139 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.705745224 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 3605129605 ps |
CPU time | 3.71 seconds |
Started | Jul 26 05:02:35 PM PDT 24 |
Finished | Jul 26 05:02:39 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-dd4ca099-536a-4e82-abda-84ec08bf8c56 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705745224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.705745224 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.1095213514 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 94448637093 ps |
CPU time | 390.51 seconds |
Started | Jul 26 05:02:50 PM PDT 24 |
Finished | Jul 26 05:09:20 PM PDT 24 |
Peak memory | 235152 kb |
Host | smart-a8aa6799-b249-4c71-adcf-78b1283d6a75 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095213514 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.1095213514 |
Directory | /workspace/7.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.1050370856 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 61421627 ps |
CPU time | 0.85 seconds |
Started | Jul 26 05:02:54 PM PDT 24 |
Finished | Jul 26 05:02:55 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-210e4a27-57cb-42dd-a9f9-6e05ce2d34c8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050370856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1050370856 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.17497902 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 3233886628 ps |
CPU time | 2.95 seconds |
Started | Jul 26 05:02:30 PM PDT 24 |
Finished | Jul 26 05:02:33 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-96223cc6-1ddc-4244-9ea5-f71a204609dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17497902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.17497902 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1590512690 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 5019793217 ps |
CPU time | 14.24 seconds |
Started | Jul 26 05:02:29 PM PDT 24 |
Finished | Jul 26 05:02:44 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-44f17239-1c3b-46ab-a433-436f360fe4b2 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1590512690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.1590512690 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.846439163 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 10159115249 ps |
CPU time | 29.04 seconds |
Started | Jul 26 05:02:44 PM PDT 24 |
Finished | Jul 26 05:03:14 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-a130795f-1d61-44dd-b156-dff46db7f275 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=846439163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.846439163 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.1022979322 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 4482876047 ps |
CPU time | 13.88 seconds |
Started | Jul 26 05:02:41 PM PDT 24 |
Finished | Jul 26 05:02:55 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-c9ccee2e-b005-441b-b046-5b24ad576187 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022979322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.1022979322 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.2557527792 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 110252829 ps |
CPU time | 0.71 seconds |
Started | Jul 26 05:02:42 PM PDT 24 |
Finished | Jul 26 05:02:43 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-e8f66f1c-89e5-41dc-b6ef-2df219546cbc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557527792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2557527792 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1374085712 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 1641743275 ps |
CPU time | 3.45 seconds |
Started | Jul 26 05:02:42 PM PDT 24 |
Finished | Jul 26 05:02:45 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-dc160721-5a36-423a-946a-0083eb354f0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1374085712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1374085712 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3232643246 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 5939161486 ps |
CPU time | 3.2 seconds |
Started | Jul 26 05:02:28 PM PDT 24 |
Finished | Jul 26 05:02:32 PM PDT 24 |
Peak memory | 213696 kb |
Host | smart-2fd10f38-cdd8-40d7-88d1-4aaefb0f6179 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232643246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3232643246 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2998714322 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 2744097337 ps |
CPU time | 2.97 seconds |
Started | Jul 26 05:02:43 PM PDT 24 |
Finished | Jul 26 05:02:46 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-622285f0-d754-4bb8-a4d7-bf0d3acb85a9 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2998714322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.2998714322 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.921515730 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 2823479681 ps |
CPU time | 1.81 seconds |
Started | Jul 26 05:02:33 PM PDT 24 |
Finished | Jul 26 05:02:35 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-905af379-db95-455a-9aa1-80ae6bf4cdbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921515730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.921515730 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.1444256452 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 1824113524 ps |
CPU time | 2.12 seconds |
Started | Jul 26 05:02:49 PM PDT 24 |
Finished | Jul 26 05:02:51 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-00e87efe-ecdd-426c-912c-25c456c60bd1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444256452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1444256452 |
Directory | /workspace/9.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.2421035043 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 74115327793 ps |
CPU time | 150.06 seconds |
Started | Jul 26 05:02:46 PM PDT 24 |
Finished | Jul 26 05:05:17 PM PDT 24 |
Peak memory | 220928 kb |
Host | smart-5f040f5a-bdaa-4f7c-a46b-f39552baedf1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421035043 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.2421035043 |
Directory | /workspace/9.rv_dm_stress_all_with_rand_reset/latest |
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