Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.97 95.72 83.72 89.91 75.00 88.00 98.53 56.89


Total tests in report: 443
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
58.19 58.19 87.78 87.78 58.07 58.07 37.00 37.00 53.75 53.75 70.33 70.33 93.38 93.38 7.02 7.02 /workspace/coverage/default/48.rv_dm_stress_all.2774197639
71.22 13.03 89.89 2.11 72.00 13.93 60.58 23.58 57.50 3.75 76.83 6.50 94.64 1.26 47.07 40.05 /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.560326502
78.04 6.82 93.31 3.42 77.93 5.93 79.82 19.24 67.50 10.00 83.00 6.17 96.11 1.47 48.60 1.53 /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3485001224
79.46 1.42 93.36 0.05 78.21 0.28 80.64 0.82 75.00 7.50 83.50 0.50 96.64 0.53 48.85 0.26 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.202866374
80.48 1.02 93.46 0.10 79.72 1.52 82.49 1.85 75.00 0.00 84.00 0.50 96.64 0.00 52.04 3.19 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.4013986645
81.19 0.71 93.56 0.10 79.86 0.14 86.67 4.18 75.00 0.00 84.17 0.17 96.64 0.00 52.42 0.38 /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.963940889
81.53 0.35 94.16 0.60 80.55 0.69 86.67 0.00 75.00 0.00 85.17 1.00 96.64 0.00 52.55 0.13 /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.3584972776
81.87 0.34 94.32 0.15 80.55 0.00 88.19 1.52 75.00 0.00 85.50 0.33 96.64 0.00 52.93 0.38 /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1191555535
82.10 0.22 94.32 0.00 81.10 0.55 88.72 0.53 75.00 0.00 85.50 0.00 96.74 0.11 53.32 0.38 /workspace/coverage/default/39.rv_dm_alert_test.498270814
82.30 0.20 94.77 0.45 81.52 0.41 88.80 0.08 75.00 0.00 85.83 0.33 96.74 0.00 53.44 0.13 /workspace/coverage/default/0.rv_dm_abstractcmd_status.380047925
82.47 0.17 95.07 0.30 81.93 0.41 88.80 0.00 75.00 0.00 86.33 0.50 96.74 0.00 53.44 0.00 /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1566370977
82.64 0.16 95.37 0.30 82.34 0.41 88.88 0.08 75.00 0.00 86.67 0.33 96.74 0.00 53.44 0.00 /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.3394139002
82.78 0.14 95.37 0.00 82.76 0.41 89.09 0.21 75.00 0.00 86.67 0.00 96.85 0.11 53.70 0.26 /workspace/coverage/default/0.rv_dm_sec_cm.2728557942
82.89 0.11 95.52 0.15 82.90 0.14 89.09 0.00 75.00 0.00 87.17 0.50 96.85 0.00 53.70 0.00 /workspace/coverage/default/0.rv_dm_cmderr_exception.3452124521
82.99 0.11 95.52 0.00 82.90 0.00 89.83 0.74 75.00 0.00 87.17 0.00 96.85 0.00 53.70 0.00 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.489479300
83.08 0.09 95.52 0.00 82.90 0.00 89.83 0.00 75.00 0.00 87.17 0.00 97.48 0.63 53.70 0.00 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3539526564
83.17 0.09 95.57 0.05 83.31 0.41 89.83 0.00 75.00 0.00 87.33 0.17 97.48 0.00 53.70 0.00 /workspace/coverage/default/0.rv_dm_dmi_failed_op.2947262119
83.25 0.08 95.57 0.00 83.31 0.00 89.83 0.00 75.00 0.00 87.33 0.00 98.00 0.53 53.70 0.00 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1236910426
83.32 0.07 95.62 0.05 83.45 0.14 89.83 0.00 75.00 0.00 87.67 0.33 98.00 0.00 53.70 0.00 /workspace/coverage/default/0.rv_dm_rom_read_access.369821026
83.38 0.05 95.62 0.00 83.45 0.00 89.83 0.00 75.00 0.00 87.67 0.00 98.00 0.00 54.08 0.38 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3917905573
83.43 0.05 95.62 0.00 83.45 0.00 89.83 0.00 75.00 0.00 87.67 0.00 98.00 0.00 54.46 0.38 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4213931420
83.49 0.05 95.62 0.00 83.45 0.00 89.83 0.00 75.00 0.00 87.67 0.00 98.00 0.00 54.85 0.38 /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.797521123
83.54 0.05 95.62 0.00 83.45 0.00 89.83 0.00 75.00 0.00 87.67 0.00 98.00 0.00 55.23 0.38 /workspace/coverage/default/30.rv_dm_stress_all.3006253419
83.59 0.05 95.67 0.05 83.59 0.14 89.83 0.00 75.00 0.00 87.83 0.17 98.00 0.00 55.23 0.00 /workspace/coverage/default/0.rv_dm_hartsel_warl.2497776569
83.64 0.05 95.67 0.00 83.59 0.00 89.91 0.08 75.00 0.00 87.83 0.00 98.00 0.00 55.48 0.26 /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.4068141285
83.68 0.04 95.67 0.00 83.59 0.00 89.91 0.00 75.00 0.00 87.83 0.00 98.00 0.00 55.74 0.26 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2403740549
83.71 0.04 95.67 0.00 83.59 0.00 89.91 0.00 75.00 0.00 87.83 0.00 98.00 0.00 55.99 0.26 /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.4090784231
83.75 0.04 95.67 0.00 83.59 0.00 89.91 0.00 75.00 0.00 87.83 0.00 98.00 0.00 56.25 0.26 /workspace/coverage/default/32.rv_dm_stress_all.4087162206
83.79 0.04 95.67 0.00 83.59 0.00 89.91 0.00 75.00 0.00 87.83 0.00 98.00 0.00 56.51 0.26 /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2547919289
83.82 0.03 95.72 0.05 83.59 0.00 89.91 0.00 75.00 0.00 88.00 0.17 98.00 0.00 56.51 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4148484489
83.85 0.03 95.72 0.00 83.59 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.21 0.21 56.51 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2691178117
83.88 0.03 95.72 0.00 83.59 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.21 56.51 0.00 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.219397755
83.90 0.02 95.72 0.00 83.72 0.14 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.00 56.51 0.00 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1525892008
83.92 0.02 95.72 0.00 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.00 56.63 0.13 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2224422034
83.93 0.02 95.72 0.00 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.00 56.76 0.13 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.919322448
83.95 0.02 95.72 0.00 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.00 56.89 0.13 /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.976177301
83.97 0.02 95.72 0.00 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.53 0.11 56.89 0.00 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2423332607

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3460369801
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.43871656
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3927908405
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1525724375
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.765549249
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4208922754
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3509630893
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.453499595
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3988034251
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.55348120
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.382505413
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.871570758
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1130758229
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3891846476
/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2529890741
/workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3054299910
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2776426067
/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1171776378
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3964424553
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2315729184
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.770530529
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.544715418
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2424404797
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3624138940
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.911818640
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2571668644
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3711710318
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.770069069
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4167407809
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1835520032
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1632352436
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1649349177
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3821262297
/workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4032219204
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3011014785
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.85311307
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1469059166
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2750229817
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1638453134
/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.429770336
/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.649212908
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1521975655
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4275216593
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2702772987
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1348365646
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4111433829
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2556850002
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.568136429
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3450711199
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3806998878
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1648292962
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2085391375
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1785986297
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.576133950
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3614417477
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2669649335
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.262145708
/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.867396698
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3078378228
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3447507469
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1459270939
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1063338633
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.716315330
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2981905030
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3056971038
/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1396670824
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2050057825
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1212950049
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2598910591
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4112384559
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1958117557
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1030805077
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3185100347
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1738068700
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4088121677
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4267732857
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3790521151
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.840993911
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.899121412
/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3975412697
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.763992306
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2209611702
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1712105153
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2144515246
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4115629012
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1433765240
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.4283278481
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1321317790
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1277463491
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3479181734
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3996792311
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4138647420
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4159661634
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.714878747
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3110664747
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.268466957
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1207175983
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3664222574
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2639607060
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3523325694
/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3815122809
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3235200330
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3419922303
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2696649605
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3799701605
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.927252773
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1880527555
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1847390338
/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1706954756
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3595781873
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.987918062
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3714209974
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.106354491
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1401142810
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3983155585
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3992244845
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2243688515
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2745135461
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1735626517
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1236724683
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1382557778
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.939490449
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1402305452
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1835163777
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2726538916
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2117410310
/workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.371748157
/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.52897599
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3522524057
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1014419628
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.555644178
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2766716959
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.677670955
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3006361585
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3105595002
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1826957581
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2403287994
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1094974261
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3546992649
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.553554502
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.834571648
/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2564908311
/workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.141039619
/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2322364433
/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.4185874437
/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1123487349
/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.380783376
/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2601199512
/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2403587205
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/workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.2421035043



Total test records in report: 443
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1602486187 Jul 26 05:02:40 PM PDT 24 Jul 26 05:03:01 PM PDT 24 8294716052 ps
T2 /workspace/coverage/default/0.rv_dm_sba_tl_access.2441020576 Jul 26 05:02:24 PM PDT 24 Jul 26 05:02:34 PM PDT 24 5562659672 ps
T3 /workspace/coverage/default/48.rv_dm_stress_all.2774197639 Jul 26 05:03:03 PM PDT 24 Jul 26 05:03:13 PM PDT 24 7325514837 ps
T15 /workspace/coverage/default/4.rv_dm_sba_tl_access.1093575312 Jul 26 05:02:30 PM PDT 24 Jul 26 05:02:31 PM PDT 24 749848519 ps
T38 /workspace/coverage/default/39.rv_dm_alert_test.498270814 Jul 26 05:03:04 PM PDT 24 Jul 26 05:03:05 PM PDT 24 65630556 ps
T23 /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3018050256 Jul 26 05:02:35 PM PDT 24 Jul 26 05:02:37 PM PDT 24 901265323 ps
T24 /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.17497902 Jul 26 05:02:30 PM PDT 24 Jul 26 05:02:33 PM PDT 24 3233886628 ps
T39 /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4109716144 Jul 26 05:02:57 PM PDT 24 Jul 26 05:03:01 PM PDT 24 1967574368 ps
T33 /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3485001224 Jul 26 05:02:34 PM PDT 24 Jul 26 05:02:37 PM PDT 24 1542579431 ps
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T222 /workspace/coverage/default/19.rv_dm_sba_tl_access.4256424418 Jul 26 05:02:59 PM PDT 24 Jul 26 05:03:03 PM PDT 24 2131088442 ps
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T227 /workspace/coverage/default/35.rv_dm_alert_test.592052027 Jul 26 05:02:52 PM PDT 24 Jul 26 05:02:53 PM PDT 24 51924158 ps
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T230 /workspace/coverage/default/15.rv_dm_stress_all.969957794 Jul 26 05:02:37 PM PDT 24 Jul 26 05:02:44 PM PDT 24 3686024737 ps
T231 /workspace/coverage/default/2.rv_dm_sba_tl_access.1711105651 Jul 26 05:02:36 PM PDT 24 Jul 26 05:02:39 PM PDT 24 1986163988 ps
T137 /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.4090784231 Jul 26 05:02:43 PM PDT 24 Jul 26 05:02:48 PM PDT 24 1575115700 ps
T232 /workspace/coverage/default/36.rv_dm_alert_test.2980484429 Jul 26 05:02:53 PM PDT 24 Jul 26 05:02:54 PM PDT 24 35163797 ps
T233 /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1518521574 Jul 26 05:02:53 PM PDT 24 Jul 26 05:03:11 PM PDT 24 9781420531 ps
T234 /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3464903863 Jul 26 05:02:44 PM PDT 24 Jul 26 05:02:52 PM PDT 24 2626893429 ps
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T236 /workspace/coverage/default/33.rv_dm_alert_test.694569817 Jul 26 05:02:54 PM PDT 24 Jul 26 05:03:00 PM PDT 24 114638790 ps
T237 /workspace/coverage/default/5.rv_dm_sba_tl_access.3572045695 Jul 26 05:02:44 PM PDT 24 Jul 26 05:02:47 PM PDT 24 1252113512 ps
T238 /workspace/coverage/default/49.rv_dm_alert_test.1994573565 Jul 26 05:02:54 PM PDT 24 Jul 26 05:02:55 PM PDT 24 39702164 ps
T239 /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.858735843 Jul 26 05:02:28 PM PDT 24 Jul 26 05:02:40 PM PDT 24 7021921906 ps
T140 /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.795791337 Jul 26 05:03:05 PM PDT 24 Jul 26 05:03:11 PM PDT 24 3731175156 ps
T240 /workspace/coverage/default/47.rv_dm_alert_test.3020824521 Jul 26 05:03:16 PM PDT 24 Jul 26 05:03:17 PM PDT 24 105645347 ps
T241 /workspace/coverage/default/16.rv_dm_alert_test.3375927555 Jul 26 05:02:55 PM PDT 24 Jul 26 05:02:56 PM PDT 24 66831028 ps
T242 /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2029536648 Jul 26 05:02:48 PM PDT 24 Jul 26 05:02:58 PM PDT 24 6921139465 ps
T243 /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3256997966 Jul 26 05:02:27 PM PDT 24 Jul 26 05:02:30 PM PDT 24 713659611 ps
T148 /workspace/coverage/default/13.rv_dm_sba_tl_access.4188025795 Jul 26 05:02:39 PM PDT 24 Jul 26 05:02:49 PM PDT 24 10939338390 ps
T244 /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.4095578697 Jul 26 05:02:38 PM PDT 24 Jul 26 05:05:19 PM PDT 24 87268012911 ps
T245 /workspace/coverage/default/23.rv_dm_alert_test.1813694568 Jul 26 05:02:41 PM PDT 24 Jul 26 05:02:42 PM PDT 24 90297738 ps
T246 /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1712541768 Jul 26 05:02:27 PM PDT 24 Jul 26 05:02:30 PM PDT 24 514701536 ps
T247 /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1590512690 Jul 26 05:02:29 PM PDT 24 Jul 26 05:02:44 PM PDT 24 5019793217 ps
T248 /workspace/coverage/default/14.rv_dm_sba_tl_access.2852944135 Jul 26 05:02:50 PM PDT 24 Jul 26 05:03:21 PM PDT 24 11318179909 ps
T249 /workspace/coverage/default/11.rv_dm_alert_test.2384374227 Jul 26 05:03:09 PM PDT 24 Jul 26 05:03:09 PM PDT 24 70671668 ps
T250 /workspace/coverage/default/14.rv_dm_stress_all.871679902 Jul 26 05:02:51 PM PDT 24 Jul 26 05:02:55 PM PDT 24 9032468556 ps
T141 /workspace/coverage/default/1.rv_dm_sba_tl_access.1651081996 Jul 26 05:02:27 PM PDT 24 Jul 26 05:02:34 PM PDT 24 2512867755 ps
T251 /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2626580343 Jul 26 05:02:38 PM PDT 24 Jul 26 05:02:41 PM PDT 24 2326996502 ps
T252 /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3844091068 Jul 26 05:02:46 PM PDT 24 Jul 26 05:02:50 PM PDT 24 1121638886 ps
T145 /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.976177301 Jul 26 05:02:38 PM PDT 24 Jul 26 05:03:11 PM PDT 24 10774384119 ps
T253 /workspace/coverage/default/0.rv_dm_debug_disabled.3010681850 Jul 26 05:02:24 PM PDT 24 Jul 26 05:02:25 PM PDT 24 79129583 ps
T254 /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.518604832 Jul 26 05:02:39 PM PDT 24 Jul 26 05:03:08 PM PDT 24 10357184920 ps
T55 /workspace/coverage/default/1.rv_dm_sec_cm.2038779015 Jul 26 05:02:27 PM PDT 24 Jul 26 05:02:29 PM PDT 24 731898040 ps
T255 /workspace/coverage/default/1.rv_dm_stress_all.2707096321 Jul 26 05:02:43 PM PDT 24 Jul 26 05:02:59 PM PDT 24 5291122424 ps
T138 /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.797521123 Jul 26 05:02:31 PM PDT 24 Jul 26 05:02:35 PM PDT 24 4785060563 ps
T256 /workspace/coverage/default/15.rv_dm_sba_tl_access.2185284812 Jul 26 05:02:39 PM PDT 24 Jul 26 05:02:43 PM PDT 24 4231969318 ps
T257 /workspace/coverage/default/1.rv_dm_smoke.2780988035 Jul 26 05:02:24 PM PDT 24 Jul 26 05:02:29 PM PDT 24 2604278494 ps
T258 /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2140860626 Jul 26 05:02:27 PM PDT 24 Jul 26 05:02:29 PM PDT 24 3203648390 ps
T259 /workspace/coverage/default/9.rv_dm_sba_tl_access.921515730 Jul 26 05:02:33 PM PDT 24 Jul 26 05:02:35 PM PDT 24 2823479681 ps
T260 /workspace/coverage/default/0.rv_dm_alert_test.1986689448 Jul 26 05:02:47 PM PDT 24 Jul 26 05:02:47 PM PDT 24 206286215 ps
T10 /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.3584972776 Jul 26 05:02:53 PM PDT 24 Jul 26 05:09:37 PM PDT 24 118748404378 ps
T261 /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1470500544 Jul 26 05:02:37 PM PDT 24 Jul 26 05:03:47 PM PDT 24 22097549153 ps
T262 /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3727673764 Jul 26 05:02:25 PM PDT 24 Jul 26 05:02:26 PM PDT 24 315669128 ps
T263 /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3232643246 Jul 26 05:02:28 PM PDT 24 Jul 26 05:02:32 PM PDT 24 5939161486 ps
T149 /workspace/coverage/default/43.rv_dm_stress_all.3527323963 Jul 26 05:02:50 PM PDT 24 Jul 26 05:03:01 PM PDT 24 6539294155 ps
T264 /workspace/coverage/default/20.rv_dm_alert_test.2190171856 Jul 26 05:02:39 PM PDT 24 Jul 26 05:02:40 PM PDT 24 34548720 ps
T265 /workspace/coverage/default/3.rv_dm_sba_tl_access.1539064330 Jul 26 05:02:51 PM PDT 24 Jul 26 05:02:58 PM PDT 24 2846528713 ps
T46 /workspace/coverage/default/0.rv_dm_dmi_failed_op.2947262119 Jul 26 05:02:24 PM PDT 24 Jul 26 05:02:25 PM PDT 24 553454747 ps
T266 /workspace/coverage/default/22.rv_dm_stress_all.1692772144 Jul 26 05:02:42 PM PDT 24 Jul 26 05:02:50 PM PDT 24 2578098062 ps
T133 /workspace/coverage/default/7.rv_dm_stress_all.705745224 Jul 26 05:02:35 PM PDT 24 Jul 26 05:02:39 PM PDT 24 3605129605 ps
T267 /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.415199417 Jul 26 05:02:26 PM PDT 24 Jul 26 05:02:28 PM PDT 24 1048748148 ps
T268 /workspace/coverage/default/2.rv_dm_alert_test.3945661714 Jul 26 05:02:27 PM PDT 24 Jul 26 05:02:28 PM PDT 24 39935314 ps
T269 /workspace/coverage/default/46.rv_dm_alert_test.1939634341 Jul 26 05:03:02 PM PDT 24 Jul 26 05:03:03 PM PDT 24 93314491 ps
T270 /workspace/coverage/default/4.rv_dm_alert_test.1194555168 Jul 26 05:02:27 PM PDT 24 Jul 26 05:02:28 PM PDT 24 88040608 ps
T271 /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.451957784 Jul 26 05:02:40 PM PDT 24 Jul 26 05:03:26 PM PDT 24 28678931006 ps
T11 /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.192763389 Jul 26 05:02:50 PM PDT 24 Jul 26 05:24:31 PM PDT 24 821433454075 ps
T272 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2575423873 Jul 26 05:02:26 PM PDT 24 Jul 26 05:02:28 PM PDT 24 549501505 ps
T273 /workspace/coverage/default/43.rv_dm_alert_test.2666955793 Jul 26 05:02:55 PM PDT 24 Jul 26 05:02:55 PM PDT 24 68296108 ps
T274 /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4184110085 Jul 26 05:02:44 PM PDT 24 Jul 26 05:03:05 PM PDT 24 7222800918 ps
T70 /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.1095213514 Jul 26 05:02:50 PM PDT 24 Jul 26 05:09:20 PM PDT 24 94448637093 ps
T275 /workspace/coverage/default/44.rv_dm_alert_test.4029202395 Jul 26 05:03:16 PM PDT 24 Jul 26 05:03:18 PM PDT 24 162871920 ps
T276 /workspace/coverage/default/26.rv_dm_alert_test.2714712977 Jul 26 05:03:03 PM PDT 24 Jul 26 05:03:03 PM PDT 24 67877204 ps
T127 /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2228104573 Jul 26 05:02:30 PM PDT 24 Jul 26 05:02:39 PM PDT 24 2968476643 ps
T277 /workspace/coverage/default/3.rv_dm_stress_all.2849393839 Jul 26 05:02:33 PM PDT 24 Jul 26 05:02:38 PM PDT 24 8475864636 ps
T278 /workspace/coverage/default/27.rv_dm_stress_all.2535056887 Jul 26 05:02:54 PM PDT 24 Jul 26 05:03:05 PM PDT 24 12016123728 ps
T279 /workspace/coverage/default/18.rv_dm_sba_tl_access.433328368 Jul 26 05:02:55 PM PDT 24 Jul 26 05:03:03 PM PDT 24 4342950489 ps
T280 /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2915677701 Jul 26 05:02:20 PM PDT 24 Jul 26 05:02:21 PM PDT 24 162663581 ps
T281 /workspace/coverage/default/5.rv_dm_alert_test.3056665822 Jul 26 05:02:37 PM PDT 24 Jul 26 05:02:38 PM PDT 24 63467736 ps
T282 /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3065830467 Jul 26 05:02:23 PM PDT 24 Jul 26 05:02:27 PM PDT 24 4188116012 ps
T283 /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2179913069 Jul 26 05:02:37 PM PDT 24 Jul 26 05:02:43 PM PDT 24 3245053523 ps
T284 /workspace/coverage/default/40.rv_dm_alert_test.773438488 Jul 26 05:02:50 PM PDT 24 Jul 26 05:02:51 PM PDT 24 173945203 ps
T285 /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3119556346 Jul 26 05:02:32 PM PDT 24 Jul 26 05:02:42 PM PDT 24 15779566401 ps
T286 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.4140567272 Jul 26 05:46:09 PM PDT 24 Jul 26 05:46:19 PM PDT 24 16148983942 ps
T71 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.919322448 Jul 26 05:46:12 PM PDT 24 Jul 26 05:46:20 PM PDT 24 1023212799 ps
T287 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3891846476 Jul 26 05:45:49 PM PDT 24 Jul 26 05:45:50 PM PDT 24 73823430 ps
T89 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.4013986645 Jul 26 05:46:06 PM PDT 24 Jul 26 05:46:26 PM PDT 24 4572108957 ps
T63 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3659526867 Jul 26 05:46:08 PM PDT 24 Jul 26 05:47:15 PM PDT 24 74149786746 ps
T72 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.714878747 Jul 26 05:46:25 PM PDT 24 Jul 26 05:46:28 PM PDT 24 121879748 ps
T79 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3539526564 Jul 26 05:46:24 PM PDT 24 Jul 26 05:46:32 PM PDT 24 1682733577 ps
T288 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.677670955 Jul 26 05:46:01 PM PDT 24 Jul 26 05:47:25 PM PDT 24 60751449796 ps
T289 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1030805077 Jul 26 05:46:16 PM PDT 24 Jul 26 05:46:19 PM PDT 24 98107430 ps
T66 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1382557778 Jul 26 05:45:47 PM PDT 24 Jul 26 05:45:50 PM PDT 24 934331847 ps
T64 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1534174681 Jul 26 05:46:09 PM PDT 24 Jul 26 05:46:32 PM PDT 24 21368355217 ps
T80 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3054299910 Jul 26 05:45:46 PM PDT 24 Jul 26 05:58:48 PM PDT 24 140989401669 ps
T290 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4267732857 Jul 26 05:46:24 PM PDT 24 Jul 26 05:46:27 PM PDT 24 1274026393 ps
T81 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3776500375 Jul 26 05:45:57 PM PDT 24 Jul 26 05:45:59 PM PDT 24 173717260 ps
T82 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.805507852 Jul 26 05:46:05 PM PDT 24 Jul 26 05:46:07 PM PDT 24 247322851 ps
T83 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.380783376 Jul 26 05:45:59 PM PDT 24 Jul 26 05:47:09 PM PDT 24 5122662127 ps
T84 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.564538187 Jul 26 05:46:01 PM PDT 24 Jul 26 05:46:09 PM PDT 24 936889734 ps
T291 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1212950049 Jul 26 05:46:14 PM PDT 24 Jul 26 05:46:17 PM PDT 24 5298007912 ps
T67 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.927252773 Jul 26 05:46:24 PM PDT 24 Jul 26 05:46:25 PM PDT 24 249640979 ps
T68 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1826957581 Jul 26 05:46:01 PM PDT 24 Jul 26 05:46:02 PM PDT 24 290329747 ps
T85 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2726538916 Jul 26 05:45:58 PM PDT 24 Jul 26 05:46:02 PM PDT 24 153148727 ps
T119 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3235200330 Jul 26 05:46:22 PM PDT 24 Jul 26 05:46:25 PM PDT 24 297394938 ps
T120 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.489479300 Jul 26 05:45:48 PM PDT 24 Jul 26 05:46:10 PM PDT 24 29636784884 ps
T292 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1348365646 Jul 26 05:46:05 PM PDT 24 Jul 26 05:46:35 PM PDT 24 14877834960 ps
T293 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3450711199 Jul 26 05:46:04 PM PDT 24 Jul 26 05:46:10 PM PDT 24 231754566 ps
T294 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.546845234 Jul 26 05:45:56 PM PDT 24 Jul 26 05:46:02 PM PDT 24 6396747282 ps
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