Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 6211888 1 T1 12 T3 645000 T4 3
full_word 1486129 1 T1 5 T3 89557 T4 1



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 7697717 1 T1 17 T3 734557 T4 4
auto[TlIntgErrCmd] 100 1 T111 1 T112 3 T113 5
auto[TlIntgErrData] 93 1 T111 4 T112 3 T113 6
auto[TlIntgErrBoth] 107 1 T111 5 T112 4 T113 9



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 904779 1 T1 1 T3 43158 T19 89931
auto[1] 6793238 1 T1 16 T3 691399 T4 4



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 408139 1 T3 22534 T19 46016 T28 5
auto[TlIntgErrNone] partial auto[1] 5803479 1 T1 12 T3 622466 T4 3
auto[TlIntgErrNone] full_word auto[0] 496493 1 T1 1 T3 20624 T19 43915
auto[TlIntgErrNone] full_word auto[1] 989606 1 T1 4 T3 68933 T4 1
auto[TlIntgErrCmd] partial auto[0] 43 1 T112 1 T113 1 T155 1
auto[TlIntgErrCmd] partial auto[1] 51 1 T111 1 T112 1 T113 4
auto[TlIntgErrCmd] full_word auto[0] 2 1 T112 1 T161 1 - -
auto[TlIntgErrCmd] full_word auto[1] 4 1 T155 1 T154 1 T157 1
auto[TlIntgErrData] partial auto[0] 39 1 T111 3 T112 3 T113 2
auto[TlIntgErrData] partial auto[1] 41 1 T113 1 T155 2 T162 2
auto[TlIntgErrData] full_word auto[0] 11 1 T111 1 T113 3 T155 1
auto[TlIntgErrData] full_word auto[1] 2 1 T162 1 T163 1 - -
auto[TlIntgErrBoth] partial auto[0] 46 1 T111 3 T113 5 T155 6
auto[TlIntgErrBoth] partial auto[1] 50 1 T111 2 T112 3 T113 3
auto[TlIntgErrBoth] full_word auto[0] 6 1 T163 1 T156 2 T158 2
auto[TlIntgErrBoth] full_word auto[1] 5 1 T112 1 T113 1 T154 1

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