Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00


Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 26612541 26611109 0 0
selKnown1 137955814 137954382 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 26612541 26611109 0 0
T1 27113 27109 0 0
T2 484 480 0 0
T3 478042 478038 0 0
T4 16398 16394 0 0
T5 19472 19468 0 0
T19 486706 486702 0 0
T26 5743 5739 0 0
T27 893 889 0 0
T28 2707 2703 0 0
T29 3080 3076 0 0
T36 0 8 0 0
T38 0 6 0 0
T39 0 8 0 0
T49 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 137955814 137954382 0 0
T1 83692 83688 0 0
T2 3460 3456 0 0
T3 1006584 1006581 0 0
T4 271054 271050 0 0
T5 382430 382426 0 0
T19 348912 348909 0 0
T26 126559 126555 0 0
T27 2208 2204 0 0
T28 21989 21985 0 0
T29 55711 55707 0 0
T36 0 6 0 0
T38 0 6 0 0
T39 0 6 0 0
T49 0 4 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 11248463 11248215 0 0
selKnown1 122592143 122591895 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 11248463 11248215 0 0
T1 13552 13551 0 0
T2 241 240 0 0
T3 239012 239011 0 0
T4 8193 8192 0 0
T5 9731 9730 0 0
T19 243342 243341 0 0
T26 2850 2849 0 0
T27 445 444 0 0
T28 1352 1351 0 0
T29 1539 1538 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 122592143 122591895 0 0
T1 70132 70131 0 0
T2 3217 3216 0 0
T3 767560 767560 0 0
T4 262849 262848 0 0
T5 372689 372688 0 0
T19 105558 105558 0 0
T26 123667 123666 0 0
T27 1761 1760 0 0
T28 20635 20634 0 0
T29 54170 54169 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 760 512 0 0
selKnown1 698 450 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 760 512 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 9 8 0 0
T4 6 5 0 0
T5 5 4 0 0
T19 10 9 0 0
T26 21 20 0 0
T27 1 0 0 0
T28 1 0 0 0
T29 1 0 0 0
T36 0 4 0 0
T38 0 3 0 0
T39 0 4 0 0
T49 0 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 698 450 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 6 5 0 0
T5 5 4 0 0
T19 6 5 0 0
T26 21 20 0 0
T27 1 0 0 0
T28 1 0 0 0
T29 1 0 0 0
T36 0 3 0 0
T38 0 3 0 0
T39 0 3 0 0
T49 0 2 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 15361354 15360886 0 0
selKnown1 15361138 15360670 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 15361354 15360886 0 0
T1 13552 13551 0 0
T2 241 240 0 0
T3 239012 239011 0 0
T4 8193 8192 0 0
T5 9731 9730 0 0
T19 243342 243341 0 0
T26 2851 2850 0 0
T27 446 445 0 0
T28 1353 1352 0 0
T29 1539 1538 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 15361138 15360670 0 0
T1 13552 13551 0 0
T2 241 240 0 0
T3 239012 239011 0 0
T4 8193 8192 0 0
T5 9731 9730 0 0
T19 243342 243341 0 0
T26 2850 2849 0 0
T27 445 444 0 0
T28 1352 1351 0 0
T29 1539 1538 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1964 1496 0 0
selKnown1 1835 1367 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1964 1496 0 0
T1 5 4 0 0
T2 1 0 0 0
T3 9 8 0 0
T4 6 5 0 0
T5 5 4 0 0
T19 12 11 0 0
T26 21 20 0 0
T27 1 0 0 0
T28 1 0 0 0
T29 1 0 0 0
T36 0 4 0 0
T38 0 3 0 0
T39 0 4 0 0
T49 0 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1835 1367 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 6 5 0 0
T5 5 4 0 0
T19 6 5 0 0
T26 21 20 0 0
T27 1 0 0 0
T28 1 0 0 0
T29 1 0 0 0
T36 0 3 0 0
T38 0 3 0 0
T39 0 3 0 0
T49 0 2 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%