Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1029405	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1247172

1

T3

3

T8

2

T4

91737

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	690711	1			T3	3		T8	2		T4	26201
values[0x0]	462011	1			T8	2		T4	43329		T5	6
values[0x1]	1123855	1			T3	4		T4	132002		T5	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	456133	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1820444

1

T3

5

T8

3

T4

161579

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9422	1			T4	771		T9	145		T15	1
valid_sources[0x01]	8740	1			T4	824		T9	131		T20	204
valid_sources[0x02]	9321	1			T4	840		T9	94		T177	1
valid_sources[0x03]	8942	1			T4	817		T9	105		T20	242
valid_sources[0x04]	8963	1			T4	756		T9	96		T15	2
valid_sources[0x05]	9477	1			T4	750		T9	142		T20	235
valid_sources[0x06]	8722	1			T4	804		T9	135		T38	1
valid_sources[0x07]	8532	1			T4	771		T9	130		T20	193
valid_sources[0x08]	9934	1			T4	763		T9	117		T20	192
valid_sources[0x09]	8966	1			T4	828		T9	107		T20	190
valid_sources[0x0a]	9498	1			T4	828		T9	131		T38	1
valid_sources[0x0b]	8590	1			T4	819		T9	142		T42	1
valid_sources[0x0c]	8410	1			T4	781		T9	154		T23	5
valid_sources[0x0d]	8464	1			T4	792		T9	106		T13	1
valid_sources[0x0e]	8901	1			T4	793		T9	104		T20	223
valid_sources[0x0f]	8531	1			T4	802		T9	114		T23	1
valid_sources[0x10]	8523	1			T4	748		T9	139		T146	5
valid_sources[0x11]	8780	1			T4	770		T9	108		T160	2
valid_sources[0x12]	8532	1			T4	749		T9	141		T69	3
valid_sources[0x13]	8992	1			T4	823		T9	124		T20	225
valid_sources[0x14]	9314	1			T4	776		T9	115		T178	3
valid_sources[0x15]	9104	1			T4	779		T9	115		T20	226
valid_sources[0x16]	8362	1			T4	785		T9	102		T15	2
valid_sources[0x17]	8653	1			T4	775		T9	110		T121	5
valid_sources[0x18]	9607	1			T4	799		T9	107		T121	2
valid_sources[0x19]	8936	1			T4	823		T9	111		T22	2
valid_sources[0x1a]	8437	1			T4	726		T9	84		T20	177
valid_sources[0x1b]	8872	1			T4	804		T9	114		T20	192
valid_sources[0x1c]	8738	1			T4	811		T9	105		T15	1
valid_sources[0x1d]	8705	1			T4	822		T9	146		T20	212
valid_sources[0x1e]	15241	1			T4	765		T9	100		T41	1
valid_sources[0x1f]	8655	1			T4	742		T9	115		T20	239
valid_sources[0x20]	8241	1			T4	773		T9	113		T20	217
valid_sources[0x21]	9130	1			T4	739		T6	3		T9	125
valid_sources[0x22]	8907	1			T4	804		T9	82		T15	1
valid_sources[0x23]	8795	1			T4	818		T9	115		T20	239
valid_sources[0x24]	9314	1			T4	768		T9	100		T13	1
valid_sources[0x25]	8652	1			T4	797		T9	92		T20	200
valid_sources[0x26]	9583	1			T4	760		T9	108		T20	218
valid_sources[0x27]	8875	1			T3	7		T4	784		T9	109
valid_sources[0x28]	9426	1			T4	795		T9	128		T20	245
valid_sources[0x29]	8581	1			T4	801		T6	2		T9	131
valid_sources[0x2a]	8083	1			T4	830		T9	102		T59	2
valid_sources[0x2b]	8811	1			T4	808		T9	87		T20	203
valid_sources[0x2c]	8660	1			T4	779		T9	102		T15	1
valid_sources[0x2d]	8684	1			T4	767		T9	134		T179	2
valid_sources[0x2e]	8760	1			T4	813		T9	132		T20	248
valid_sources[0x2f]	8799	1			T4	811		T9	118		T20	224
valid_sources[0x30]	8546	1			T8	2		T4	809		T9	127
valid_sources[0x31]	8618	1			T4	784		T9	142		T20	222
valid_sources[0x32]	9295	1			T4	728		T9	92		T20	207
valid_sources[0x33]	8694	1			T4	834		T9	124		T22	1
valid_sources[0x34]	8376	1			T4	747		T9	90		T20	228
valid_sources[0x35]	9035	1			T4	826		T9	110		T20	206
valid_sources[0x36]	8660	1			T4	815		T9	132		T20	194
valid_sources[0x37]	8778	1			T4	780		T9	95		T20	214
valid_sources[0x38]	8556	1			T4	817		T9	122		T15	1
valid_sources[0x39]	8324	1			T4	798		T9	77		T15	1
valid_sources[0x3a]	8865	1			T4	843		T9	87		T20	243
valid_sources[0x3b]	8804	1			T4	794		T9	102		T20	205
valid_sources[0x3c]	8709	1			T4	840		T9	127		T20	180
valid_sources[0x3d]	8568	1			T4	800		T9	103		T180	1
valid_sources[0x3e]	8493	1			T4	802		T9	112		T20	232
valid_sources[0x3f]	10197	1			T4	775		T9	86		T13	1
valid_sources[0x40]	8926	1			T4	826		T9	106		T42	1
valid_sources[0x41]	9181	1			T4	782		T9	118		T20	211
valid_sources[0x42]	8665	1			T4	823		T9	117		T20	191
valid_sources[0x43]	8399	1			T4	814		T9	140		T20	225
valid_sources[0x44]	8757	1			T4	795		T9	112		T19	14
valid_sources[0x45]	8910	1			T4	804		T9	105		T20	233
valid_sources[0x46]	8230	1			T4	769		T9	130		T20	213
valid_sources[0x47]	8483	1			T4	784		T9	117		T20	233
valid_sources[0x48]	8586	1			T4	827		T9	99		T20	216
valid_sources[0x49]	8174	1			T4	753		T9	140		T20	218
valid_sources[0x4a]	8820	1			T4	789		T9	113		T15	1
valid_sources[0x4b]	8680	1			T4	773		T9	117		T20	215
valid_sources[0x4c]	8920	1			T4	777		T9	103		T39	4
valid_sources[0x4d]	9219	1			T4	789		T9	120		T15	1
valid_sources[0x4e]	8735	1			T4	761		T9	116		T20	201
valid_sources[0x4f]	9485	1			T4	811		T9	127		T15	1
valid_sources[0x50]	8334	1			T4	836		T9	143		T20	234
valid_sources[0x51]	8494	1			T4	732		T9	102		T13	1
valid_sources[0x52]	9378	1			T4	783		T9	103		T20	225
valid_sources[0x53]	9312	1			T4	758		T9	98		T15	1
valid_sources[0x54]	8799	1			T4	791		T9	96		T160	1
valid_sources[0x55]	9010	1			T4	838		T9	129		T13	1
valid_sources[0x56]	8394	1			T4	798		T9	112		T20	200
valid_sources[0x57]	8635	1			T4	793		T9	122		T20	190
valid_sources[0x58]	8606	1			T4	796		T9	128		T20	225
valid_sources[0x59]	8860	1			T4	815		T9	113		T22	1
valid_sources[0x5a]	8249	1			T4	793		T9	96		T15	1
valid_sources[0x5b]	8550	1			T4	751		T9	105		T178	1
valid_sources[0x5c]	8913	1			T4	802		T55	2		T9	106
valid_sources[0x5d]	9780	1			T4	872		T9	85		T10	25
valid_sources[0x5e]	8644	1			T4	776		T9	90		T20	207
valid_sources[0x5f]	8457	1			T4	792		T9	93		T17	2
valid_sources[0x60]	8826	1			T4	779		T9	115		T20	229
valid_sources[0x61]	8853	1			T4	827		T9	118		T20	224
valid_sources[0x62]	8766	1			T4	786		T9	107		T38	1
valid_sources[0x63]	8960	1			T4	757		T9	129		T20	242
valid_sources[0x64]	8803	1			T4	743		T9	110		T23	1
valid_sources[0x65]	8776	1			T4	793		T9	81		T20	224
valid_sources[0x66]	9405	1			T4	798		T9	102		T20	215
valid_sources[0x67]	8936	1			T4	771		T9	153		T20	217
valid_sources[0x68]	8916	1			T4	790		T5	19		T9	107
valid_sources[0x69]	9547	1			T4	852		T9	120		T20	248
valid_sources[0x6a]	9004	1			T4	792		T9	97		T20	187
valid_sources[0x6b]	9431	1			T8	2		T4	813		T9	92
valid_sources[0x6c]	8962	1			T4	764		T9	138		T181	21
valid_sources[0x6d]	9778	1			T4	789		T9	102		T20	208
valid_sources[0x6e]	9204	1			T4	819		T9	107		T20	232
valid_sources[0x6f]	8302	1			T4	821		T6	2		T9	103
valid_sources[0x70]	9428	1			T4	767		T9	106		T20	188
valid_sources[0x71]	9261	1			T4	763		T9	76		T20	263
valid_sources[0x72]	9000	1			T4	797		T9	135		T20	207
valid_sources[0x73]	8811	1			T4	813		T9	101		T15	1
valid_sources[0x74]	8487	1			T4	823		T9	142		T20	212
valid_sources[0x75]	10589	1			T4	782		T9	82		T20	184
valid_sources[0x76]	9303	1			T4	851		T9	107		T20	212
valid_sources[0x77]	9017	1			T4	785		T9	107		T20	194
valid_sources[0x78]	8807	1			T4	760		T9	126		T20	213
valid_sources[0x79]	8837	1			T4	773		T9	109		T20	195
valid_sources[0x7a]	8478	1			T4	854		T9	87		T20	188
valid_sources[0x7b]	9044	1			T4	810		T9	136		T180	1
valid_sources[0x7c]	8677	1			T4	812		T9	129		T20	222
valid_sources[0x7d]	8538	1			T4	733		T9	145		T20	191
valid_sources[0x7e]	8023	1			T4	740		T9	91		T20	188
valid_sources[0x7f]	8206	1			T4	752		T9	99		T20	190
valid_sources[0x80]	8917	1			T4	832		T9	116		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

469856

1

T3

2

T4

23763

T5

1

values[0x0]

all_enables

biggest_size

388804

1

T8

2

T4

33697

T5

1

values[0x1]

all_enables

biggest_size

388512

1

T3

1

T4

34277

T5

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46639	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1065502

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	285079	1			T4	36674		T9	5146		T20	10093
values[0x0]	403373	1			T3	1		T30	7		T8	4
values[0x1]	423689	1			T1	1		T2	1		T14	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24494	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1087647

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4158	1			T4	433		T50	1		T9	51
valid_sources[0x01]	3911	1			T4	185		T9	74		T140	1
valid_sources[0x02]	4516	1			T4	962		T9	81		T146	1
valid_sources[0x03]	4049	1			T4	266		T9	90		T182	2
valid_sources[0x04]	3920	1			T4	369		T9	82		T183	2
valid_sources[0x05]	4330	1			T4	372		T9	99		T183	1
valid_sources[0x06]	5506	1			T4	1122		T9	113		T177	1
valid_sources[0x07]	4416	1			T4	713		T9	80		T20	204
valid_sources[0x08]	4631	1			T4	864		T9	97		T142	1
valid_sources[0x09]	4735	1			T4	779		T9	68		T20	344
valid_sources[0x0a]	3895	1			T4	503		T9	79		T184	2
valid_sources[0x0b]	4117	1			T4	196		T9	60		T20	123
valid_sources[0x0c]	4874	1			T4	1210		T9	54		T185	1
valid_sources[0x0d]	4519	1			T8	1		T4	826		T9	72
valid_sources[0x0e]	5221	1			T4	917		T9	88		T20	8
valid_sources[0x0f]	4357	1			T31	1		T4	681		T9	83
valid_sources[0x10]	4432	1			T4	817		T9	67		T19	2
valid_sources[0x11]	4612	1			T4	731		T9	97		T20	335
valid_sources[0x12]	4353	1			T4	622		T5	1		T9	99
valid_sources[0x13]	4665	1			T4	540		T9	63		T183	1
valid_sources[0x14]	3695	1			T4	200		T9	84		T20	3
valid_sources[0x15]	4676	1			T4	940		T9	84		T20	105
valid_sources[0x16]	4238	1			T4	301		T9	92		T20	367
valid_sources[0x17]	3705	1			T4	195		T9	65		T38	1
valid_sources[0x18]	4339	1			T7	1		T4	136		T9	66
valid_sources[0x19]	4191	1			T4	658		T9	59		T20	92
valid_sources[0x1a]	3821	1			T4	349		T9	79		T10	1
valid_sources[0x1b]	4518	1			T4	1075		T6	1		T9	87
valid_sources[0x1c]	3897	1			T4	136		T9	71		T121	1
valid_sources[0x1d]	3423	1			T4	40		T9	93		T20	103
valid_sources[0x1e]	4332	1			T4	383		T9	90		T156	1
valid_sources[0x1f]	4598	1			T4	888		T9	78		T186	2
valid_sources[0x20]	4239	1			T4	437		T9	74		T146	1
valid_sources[0x21]	3696	1			T4	203		T9	89		T20	96
valid_sources[0x22]	4456	1			T37	1		T4	481		T9	68
valid_sources[0x23]	4024	1			T4	580		T9	75		T20	10
valid_sources[0x24]	4344	1			T4	683		T9	73		T46	2
valid_sources[0x25]	3743	1			T4	81		T9	93		T20	14
valid_sources[0x26]	4278	1			T4	248		T9	46		T187	1
valid_sources[0x27]	4125	1			T4	617		T9	85		T183	2
valid_sources[0x28]	3892	1			T4	313		T9	61		T20	144
valid_sources[0x29]	3649	1			T4	238		T9	87		T16	114
valid_sources[0x2a]	4958	1			T4	1043		T9	86		T20	96
valid_sources[0x2b]	3855	1			T4	250		T9	116		T188	1
valid_sources[0x2c]	3568	1			T4	178		T9	62		T189	13
valid_sources[0x2d]	3995	1			T4	357		T9	78		T20	110
valid_sources[0x2e]	4388	1			T4	700		T9	74		T20	181
valid_sources[0x2f]	4887	1			T4	1273		T9	83		T73	1
valid_sources[0x30]	4190	1			T4	426		T28	1		T6	1
valid_sources[0x31]	3785	1			T4	74		T9	80		T20	14
valid_sources[0x32]	4607	1			T4	960		T9	111		T20	178
valid_sources[0x33]	4302	1			T4	661		T9	89		T10	1
valid_sources[0x34]	4422	1			T4	477		T9	55		T20	100
valid_sources[0x35]	5166	1			T4	1396		T9	61		T41	1
valid_sources[0x36]	3936	1			T4	326		T9	69		T20	5
valid_sources[0x37]	4511	1			T4	889		T9	65		T20	2
valid_sources[0x38]	4581	1			T4	336		T9	64		T20	921
valid_sources[0x39]	4636	1			T4	689		T9	60		T69	1
valid_sources[0x3a]	3533	1			T4	3		T9	63		T20	28
valid_sources[0x3b]	4645	1			T4	964		T9	81		T190	1
valid_sources[0x3c]	4911	1			T25	12		T4	384		T9	96
valid_sources[0x3d]	3646	1			T4	102		T5	3		T9	54
valid_sources[0x3e]	5198	1			T30	21		T4	921		T9	92
valid_sources[0x3f]	4163	1			T4	205		T9	76		T191	1
valid_sources[0x40]	4370	1			T4	402		T9	65		T68	1
valid_sources[0x41]	5323	1			T4	1195		T9	90		T140	2
valid_sources[0x42]	4497	1			T4	1104		T9	80		T68	1
valid_sources[0x43]	4173	1			T4	520		T50	3		T9	84
valid_sources[0x44]	4026	1			T4	388		T9	114		T192	1
valid_sources[0x45]	5365	1			T4	1216		T9	74		T21	9
valid_sources[0x46]	3856	1			T4	94		T9	82		T22	1
valid_sources[0x47]	4300	1			T4	384		T9	46		T20	6
valid_sources[0x48]	4828	1			T4	810		T9	56		T22	1
valid_sources[0x49]	4534	1			T4	547		T9	106		T142	1
valid_sources[0x4a]	4754	1			T4	582		T9	61		T20	274
valid_sources[0x4b]	4390	1			T4	358		T9	37		T20	241
valid_sources[0x4c]	4471	1			T4	534		T9	107		T143	4
valid_sources[0x4d]	4592	1			T4	837		T9	113		T46	1
valid_sources[0x4e]	3796	1			T4	266		T50	1		T9	74
valid_sources[0x4f]	4189	1			T4	532		T9	59		T68	1
valid_sources[0x50]	4369	1			T4	528		T9	53		T193	4
valid_sources[0x51]	4141	1			T4	442		T9	101		T20	201
valid_sources[0x52]	4256	1			T3	1		T4	387		T9	112
valid_sources[0x53]	3813	1			T4	203		T5	2		T9	127
valid_sources[0x54]	4091	1			T24	1		T4	370		T80	1
valid_sources[0x55]	4579	1			T4	858		T9	60		T20	7
valid_sources[0x56]	4486	1			T8	1		T4	630		T9	59
valid_sources[0x57]	3651	1			T4	336		T9	97		T20	37
valid_sources[0x58]	4381	1			T8	1		T51	1		T4	484
valid_sources[0x59]	3682	1			T4	216		T9	70		T20	26
valid_sources[0x5a]	4195	1			T4	232		T9	89		T146	1
valid_sources[0x5b]	4255	1			T4	549		T9	43		T20	204
valid_sources[0x5c]	3987	1			T4	543		T9	44		T67	1
valid_sources[0x5d]	4399	1			T4	620		T9	103		T20	17
valid_sources[0x5e]	4831	1			T4	710		T9	65		T20	13
valid_sources[0x5f]	4268	1			T4	378		T9	67		T20	192
valid_sources[0x60]	5154	1			T4	72		T81	1		T9	84
valid_sources[0x61]	3732	1			T4	4		T9	73		T20	263
valid_sources[0x62]	4426	1			T4	724		T9	86		T41	2
valid_sources[0x63]	4421	1			T4	533		T9	67		T82	1
valid_sources[0x64]	5396	1			T4	1007		T9	69		T69	1
valid_sources[0x65]	4392	1			T4	571		T9	86		T13	2
valid_sources[0x66]	4869	1			T4	276		T9	75		T20	399
valid_sources[0x67]	4317	1			T4	622		T9	74		T20	52
valid_sources[0x68]	4363	1			T4	231		T9	55		T20	321
valid_sources[0x69]	4721	1			T4	380		T9	96		T22	1
valid_sources[0x6a]	4672	1			T4	1198		T9	61		T191	1
valid_sources[0x6b]	4996	1			T4	774		T9	88		T46	2
valid_sources[0x6c]	3836	1			T4	426		T9	121		T146	1
valid_sources[0x6d]	5185	1			T4	1312		T9	58		T42	1
valid_sources[0x6e]	4935	1			T4	999		T9	112		T184	1
valid_sources[0x6f]	4038	1			T4	490		T9	81		T15	6
valid_sources[0x70]	4697	1			T4	771		T45	10		T6	1
valid_sources[0x71]	3973	1			T4	382		T9	66		T194	1
valid_sources[0x72]	4647	1			T4	923		T9	66		T188	1
valid_sources[0x73]	4867	1			T4	1037		T9	60		T20	235
valid_sources[0x74]	4014	1			T4	405		T9	74		T46	1
valid_sources[0x75]	4705	1			T8	1		T4	837		T9	66
valid_sources[0x76]	3617	1			T4	179		T9	58		T195	1
valid_sources[0x77]	4218	1			T4	623		T9	123		T20	6
valid_sources[0x78]	4242	1			T4	443		T9	75		T20	157
valid_sources[0x79]	5204	1			T4	1000		T9	82		T184	2
valid_sources[0x7a]	5213	1			T4	1376		T9	69		T191	1
valid_sources[0x7b]	4027	1			T4	482		T6	1		T9	76
valid_sources[0x7c]	5382	1			T4	1231		T9	94		T188	8
valid_sources[0x7d]	4431	1			T4	300		T9	66		T140	1
valid_sources[0x7e]	4111	1			T4	92		T9	58		T68	1
valid_sources[0x7f]	4176	1			T4	365		T9	96		T20	144
valid_sources[0x80]	4351	1			T4	758		T9	41		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

267826

1

T4

34685

T9

4867

T20

9575

values[0x0]

all_enables

biggest_size

399442

1

T3

1

T30

3

T8

4

values[0x1]

all_enables

biggest_size

398234

1

T1

1

T2

1

T14

1