Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6113512

1

T3

4

T8

2

T4

793301

full_word

1421079

1

T3

3

T8

2

T4

115389

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7534311	1			T3	7		T8	4		T4	908690
auto[TlIntgErrCmd]	93	1			T134	2		T122	3		T135	1
auto[TlIntgErrData]	94	1			T134	4		T122	4		T135	7
auto[TlIntgErrBoth]	93	1			T134	14		T122	3		T135	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

899728

1

T3

3

T8

2

T4

54165

auto[1]

6634863

1

T3

4

T8

2

T4

854525

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	408861	1			T3	1		T8	2		T4	27657
auto[TlIntgErrNone]	partial	auto[1]	5704405	1			T3	3		T4	765644		T5	11
auto[TlIntgErrNone]	full_word	auto[0]	490743	1			T3	2		T4	26508		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	930302	1			T3	1		T8	2		T4	88881
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T134	2		T135	1		T165	3
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T122	1		T165	2		T161	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T122	1		T161	1		T169	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T122	1		T170	1		T171	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T134	2		T135	2		T165	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T134	1		T122	3		T135	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T122	1		T135	1		T170	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T134	1		T135	2		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T134	6		T122	1		T135	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T134	8		T122	1		T161	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T165	1		T172	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T122	1		T135	1		T169	1