Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	170829812	1488815	0	0
late_debug_enable_rd_A	170829812	63751	0	0
late_debug_enable_regwen_rd_A	170829812	55149	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170829812	1488815	0	0
T4	944009	202131	0	0
T5	86906	0	0	0
T9	0	26905	0	0
T16	0	104189	0	0
T20	0	53240	0	0
T26	54245	0	0	0
T28	8094	0	0	0
T29	282294	0	0	0
T45	2516	0	0	0
T54	0	90527	0	0
T55	6616	0	0	0
T74	0	301174	0	0
T75	0	156223	0	0
T76	0	130409	0	0
T77	0	213779	0	0
T78	0	66765	0	0
T79	16787	0	0	0
T80	85163	0	0	0
T81	671319	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170829812	63751	0	0
T16	327982	0	0	0
T20	247745	9256	0	0
T57	0	4912	0	0
T76	0	42040	0	0
T88	0	5	0	0
T89	0	2	0	0
T90	0	36	0	0
T91	0	13	0	0
T122	0	22	0	0
T123	0	28	0	0
T124	0	18	0	0
T125	304991	0	0	0
T126	50117	0	0	0
T127	54891	0	0	0
T128	2055	0	0	0
T129	212875	0	0	0
T130	1320	0	0	0
T131	218186	0	0	0
T132	4163	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170829812	55149	0	0
T16	327982	0	0	0
T20	247745	8268	0	0
T57	0	4345	0	0
T76	0	37554	0	0
T89	0	6	0	0
T90	0	64	0	0
T91	0	41	0	0
T100	0	4	0	0
T122	0	25	0	0
T123	0	19	0	0
T124	0	10	0	0
T125	304991	0	0	0
T126	50117	0	0	0
T127	54891	0	0	0
T128	2055	0	0	0
T129	212875	0	0	0
T130	1320	0	0	0
T131	218186	0	0	0
T132	4163	0	0	0