Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 33370626 33369196 0 0
selKnown1 119501967 119500537 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 33370626 33369196 0 0
T1 31750 31748 0 0
T2 19643 19641 0 0
T3 3257 3255 0 0
T4 31 29 0 0
T5 0 11 0 0
T6 0 12 0 0
T7 2801 2799 0 0
T8 40186 40182 0 0
T9 0 32 0 0
T14 30671 30669 0 0
T24 140390 140386 0 0
T25 24 22 0 0
T26 4 2 0 0
T28 3 1 0 0
T29 4 2 0 0
T30 477 475 0 0
T31 25032 25030 0 0
T32 32617 32615 0 0
T37 2 0 0 0
T45 2 0 0 0
T47 0 10 0 0
T50 0 12 0 0
T51 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 119501967 119500537 0 0
T1 950940 950938 0 0
T2 82877 82875 0 0
T3 9538 9536 0 0
T4 18 16 0 0
T5 0 10 0 0
T6 0 8 0 0
T7 11391 11389 0 0
T8 279058 279054 0 0
T9 0 20 0 0
T14 271737 271735 0 0
T24 183154 183151 0 0
T25 24 22 0 0
T26 4 2 0 0
T28 2 0 0 0
T29 4 2 0 0
T30 3162 3160 0 0
T31 96823 96821 0 0
T32 34687 34685 0 0
T37 2 0 0 0
T45 2 0 0 0
T47 0 20 0 0
T50 0 12 0 0
T51 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 14713442 14713194 0 0
selKnown1 100845235 100844987 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 14713442 14713194 0 0
T1 15875 15874 0 0
T2 9821 9820 0 0
T3 1628 1627 0 0
T7 1400 1399 0 0
T8 20088 20087 0 0
T14 15335 15334 0 0
T24 70194 70193 0 0
T30 238 237 0 0
T31 12516 12515 0 0
T32 16308 16307 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 100845235 100844987 0 0
T1 935065 935064 0 0
T2 73056 73055 0 0
T3 7910 7909 0 0
T7 9991 9990 0 0
T8 258962 258961 0 0
T14 256402 256401 0 0
T24 112958 112958 0 0
T30 2924 2923 0 0
T31 84307 84306 0 0
T32 18379 18378 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 800 552 0 0
selKnown1 718 470 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 800 552 0 0
T4 15 14 0 0
T5 0 5 0 0
T6 0 6 0 0
T8 4 3 0 0
T9 0 13 0 0
T24 1 0 0 0
T25 12 11 0 0
T26 2 1 0 0
T28 1 0 0 0
T29 2 1 0 0
T37 1 0 0 0
T45 1 0 0 0
T47 0 10 0 0
T50 0 6 0 0
T51 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 718 470 0 0
T4 9 8 0 0
T5 0 5 0 0
T6 0 4 0 0
T8 4 3 0 0
T9 0 10 0 0
T24 1 0 0 0
T25 12 11 0 0
T26 2 1 0 0
T28 1 0 0 0
T29 2 1 0 0
T37 1 0 0 0
T45 1 0 0 0
T47 0 10 0 0
T50 0 6 0 0
T51 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 18654503 18654036 0 0
selKnown1 18654274 18653807 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 18654503 18654036 0 0
T1 15875 15874 0 0
T2 9822 9821 0 0
T3 1629 1628 0 0
T7 1401 1400 0 0
T8 20089 20088 0 0
T14 15336 15335 0 0
T24 70194 70193 0 0
T30 239 238 0 0
T31 12516 12515 0 0
T32 16309 16308 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 18654274 18653807 0 0
T1 15875 15874 0 0
T2 9821 9820 0 0
T3 1628 1627 0 0
T7 1400 1399 0 0
T8 20088 20087 0 0
T14 15335 15334 0 0
T24 70194 70193 0 0
T30 238 237 0 0
T31 12516 12515 0 0
T32 16308 16307 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1881 1414 0 0
selKnown1 1740 1273 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1881 1414 0 0
T4 16 15 0 0
T5 0 6 0 0
T6 0 6 0 0
T8 5 4 0 0
T9 0 19 0 0
T24 1 0 0 0
T25 12 11 0 0
T26 2 1 0 0
T28 2 1 0 0
T29 2 1 0 0
T37 1 0 0 0
T45 1 0 0 0
T50 0 6 0 0
T51 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1740 1273 0 0
T4 9 8 0 0
T5 0 5 0 0
T6 0 4 0 0
T8 4 3 0 0
T9 0 10 0 0
T24 1 0 0 0
T25 12 11 0 0
T26 2 1 0 0
T28 1 0 0 0
T29 2 1 0 0
T37 1 0 0 0
T45 1 0 0 0
T47 0 10 0 0
T50 0 6 0 0
T51 1 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%