Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	737852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1034087

1

T1

2

T3

1

T4

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	614431	1			T1	1		T3	1		T4	3
values[0x0]	362927	1			T1	1		T3	2		T4	19
values[0x1]	794581	1			T4	17		T5	91235		T30	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	350247	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1421692

1

T1

2

T3

1

T4

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6846	1			T5	545		T50	81		T42	1
valid_sources[0x01]	6776	1			T5	524		T50	76		T122	1
valid_sources[0x02]	6596	1			T5	541		T50	78		T43	1
valid_sources[0x03]	6741	1			T5	608		T50	86		T11	467
valid_sources[0x04]	6615	1			T5	555		T50	78		T55	1
valid_sources[0x05]	6720	1			T5	535		T50	69		T22	2
valid_sources[0x06]	6609	1			T5	539		T6	1		T16	1
valid_sources[0x07]	6558	1			T5	578		T50	69		T123	1
valid_sources[0x08]	8673	1			T5	534		T50	68		T22	1
valid_sources[0x09]	6668	1			T5	534		T50	83		T42	2
valid_sources[0x0a]	7488	1			T5	542		T50	81		T11	480
valid_sources[0x0b]	7241	1			T5	585		T50	75		T24	2
valid_sources[0x0c]	6734	1			T5	571		T50	76		T8	3
valid_sources[0x0d]	6444	1			T5	540		T50	105		T22	2
valid_sources[0x0e]	6574	1			T5	530		T50	75		T25	1
valid_sources[0x0f]	6825	1			T5	553		T50	68		T42	3
valid_sources[0x10]	7097	1			T5	543		T50	66		T22	1
valid_sources[0x11]	6848	1			T5	537		T50	88		T22	2
valid_sources[0x12]	7038	1			T5	533		T50	93		T25	4
valid_sources[0x13]	6716	1			T5	574		T50	92		T172	1
valid_sources[0x14]	7336	1			T4	11		T5	561		T50	67
valid_sources[0x15]	6837	1			T5	528		T50	68		T43	1
valid_sources[0x16]	7070	1			T5	562		T50	73		T123	1
valid_sources[0x17]	6879	1			T5	564		T50	88		T11	485
valid_sources[0x18]	7576	1			T4	1		T5	555		T50	91
valid_sources[0x19]	6700	1			T5	556		T50	63		T43	1
valid_sources[0x1a]	7079	1			T5	566		T50	77		T43	1
valid_sources[0x1b]	6815	1			T5	557		T35	2		T50	100
valid_sources[0x1c]	6727	1			T5	521		T50	92		T42	2
valid_sources[0x1d]	6749	1			T5	567		T50	71		T22	1
valid_sources[0x1e]	7192	1			T5	550		T50	65		T11	485
valid_sources[0x1f]	6531	1			T5	534		T50	83		T23	15
valid_sources[0x20]	6810	1			T5	557		T50	92		T11	523
valid_sources[0x21]	6889	1			T5	516		T16	1		T50	99
valid_sources[0x22]	6661	1			T5	549		T16	1		T50	79
valid_sources[0x23]	6594	1			T5	509		T50	75		T11	476
valid_sources[0x24]	6459	1			T4	2		T5	584		T50	88
valid_sources[0x25]	6928	1			T5	552		T50	79		T48	1
valid_sources[0x26]	7004	1			T5	504		T50	71		T11	480
valid_sources[0x27]	6627	1			T5	540		T50	76		T157	1
valid_sources[0x28]	6448	1			T5	558		T50	81		T47	1
valid_sources[0x29]	6427	1			T5	567		T50	69		T20	4
valid_sources[0x2a]	6652	1			T5	547		T50	60		T22	1
valid_sources[0x2b]	6868	1			T5	541		T50	72		T22	1
valid_sources[0x2c]	6620	1			T5	524		T6	3		T50	67
valid_sources[0x2d]	6444	1			T3	1		T5	562		T50	82
valid_sources[0x2e]	7128	1			T5	623		T16	1		T50	77
valid_sources[0x2f]	7074	1			T5	551		T50	59		T43	1
valid_sources[0x30]	7367	1			T5	545		T50	94		T154	2
valid_sources[0x31]	6879	1			T5	581		T50	71		T47	1
valid_sources[0x32]	6880	1			T5	565		T50	76		T11	491
valid_sources[0x33]	6834	1			T5	503		T50	69		T11	527
valid_sources[0x34]	6826	1			T5	571		T50	78		T9	2
valid_sources[0x35]	6727	1			T5	526		T50	80		T10	2
valid_sources[0x36]	6587	1			T5	565		T50	86		T153	1
valid_sources[0x37]	6648	1			T5	520		T50	78		T42	3
valid_sources[0x38]	6949	1			T5	502		T50	68		T22	1
valid_sources[0x39]	6716	1			T5	588		T50	94		T45	7
valid_sources[0x3a]	6958	1			T5	551		T50	82		T46	1
valid_sources[0x3b]	7128	1			T5	522		T50	68		T173	1
valid_sources[0x3c]	6940	1			T5	561		T50	78		T22	1
valid_sources[0x3d]	6590	1			T5	536		T50	73		T11	498
valid_sources[0x3e]	7263	1			T5	562		T50	52		T22	1
valid_sources[0x3f]	6531	1			T5	547		T50	108		T17	1
valid_sources[0x40]	6901	1			T1	2		T5	552		T50	70
valid_sources[0x41]	6697	1			T5	543		T50	69		T11	499
valid_sources[0x42]	6767	1			T5	543		T50	74		T43	1
valid_sources[0x43]	6612	1			T5	589		T50	79		T11	456
valid_sources[0x44]	7501	1			T5	535		T50	90		T47	1
valid_sources[0x45]	6705	1			T5	554		T50	93		T43	1
valid_sources[0x46]	6710	1			T4	1		T5	504		T50	57
valid_sources[0x47]	6450	1			T5	557		T50	67		T22	1
valid_sources[0x48]	6630	1			T5	516		T50	87		T46	1
valid_sources[0x49]	6853	1			T5	541		T50	95		T46	1
valid_sources[0x4a]	6911	1			T5	590		T50	85		T11	515
valid_sources[0x4b]	7491	1			T5	540		T50	64		T174	1
valid_sources[0x4c]	6445	1			T5	564		T50	70		T22	1
valid_sources[0x4d]	6970	1			T5	546		T50	90		T48	1
valid_sources[0x4e]	6657	1			T5	570		T50	67		T49	1
valid_sources[0x4f]	6711	1			T5	528		T50	59		T48	1
valid_sources[0x50]	6864	1			T5	532		T50	79		T42	3
valid_sources[0x51]	7093	1			T5	522		T50	67		T11	493
valid_sources[0x52]	7067	1			T5	505		T50	75		T173	1
valid_sources[0x53]	6548	1			T5	518		T50	69		T11	510
valid_sources[0x54]	10642	1			T5	537		T50	70		T43	1
valid_sources[0x55]	7099	1			T5	532		T50	73		T25	2
valid_sources[0x56]	10921	1			T5	531		T50	68		T25	2
valid_sources[0x57]	8489	1			T5	514		T50	61		T122	2
valid_sources[0x58]	6627	1			T5	540		T50	87		T173	1
valid_sources[0x59]	6679	1			T4	1		T5	565		T6	2
valid_sources[0x5a]	6882	1			T5	535		T50	83		T17	1
valid_sources[0x5b]	6687	1			T5	566		T50	68		T22	1
valid_sources[0x5c]	6562	1			T4	5		T5	514		T50	68
valid_sources[0x5d]	6470	1			T5	561		T16	1		T50	91
valid_sources[0x5e]	6771	1			T5	547		T50	86		T43	1
valid_sources[0x5f]	6533	1			T5	580		T50	56		T42	1
valid_sources[0x60]	6637	1			T5	538		T50	75		T44	1
valid_sources[0x61]	6452	1			T5	561		T50	57		T11	463
valid_sources[0x62]	6763	1			T5	552		T50	85		T22	1
valid_sources[0x63]	6798	1			T5	501		T50	74		T43	1
valid_sources[0x64]	6568	1			T5	563		T50	78		T43	1
valid_sources[0x65]	6853	1			T5	589		T6	1		T50	80
valid_sources[0x66]	6990	1			T5	501		T16	1		T50	78
valid_sources[0x67]	6444	1			T5	559		T50	83		T11	473
valid_sources[0x68]	6684	1			T5	587		T16	1		T50	68
valid_sources[0x69]	6725	1			T5	555		T50	93		T122	3
valid_sources[0x6a]	6655	1			T5	549		T16	1		T50	77
valid_sources[0x6b]	6678	1			T5	565		T50	73		T43	2
valid_sources[0x6c]	17438	1			T5	575		T6	1		T50	79
valid_sources[0x6d]	7451	1			T5	574		T50	98		T172	1
valid_sources[0x6e]	6954	1			T5	571		T50	66		T42	2
valid_sources[0x6f]	6672	1			T5	521		T50	71		T43	1
valid_sources[0x70]	6629	1			T5	526		T16	1		T50	64
valid_sources[0x71]	6790	1			T5	559		T50	97		T11	527
valid_sources[0x72]	6890	1			T5	563		T50	59		T11	441
valid_sources[0x73]	6745	1			T5	583		T50	107		T123	1
valid_sources[0x74]	6716	1			T5	527		T50	71		T43	1
valid_sources[0x75]	6869	1			T5	564		T50	78		T22	1
valid_sources[0x76]	6619	1			T5	526		T30	10		T50	73
valid_sources[0x77]	6755	1			T5	622		T50	81		T49	2
valid_sources[0x78]	6756	1			T5	529		T50	83		T22	1
valid_sources[0x79]	6955	1			T5	513		T50	67		T46	1
valid_sources[0x7a]	6426	1			T5	557		T50	95		T11	510
valid_sources[0x7b]	6995	1			T5	547		T50	82		T154	1
valid_sources[0x7c]	6588	1			T5	560		T50	75		T7	1
valid_sources[0x7d]	6734	1			T5	535		T50	79		T42	2
valid_sources[0x7e]	6527	1			T5	553		T50	78		T22	1
valid_sources[0x7f]	6735	1			T5	585		T50	74		T42	2
valid_sources[0x80]	6933	1			T5	582		T50	69		T11	488

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

406035

1

T1

1

T4

1

T5

16810

values[0x0]

all_enables

biggest_size

314280

1

T1

1

T3

1

T4

6

values[0x1]

all_enables

biggest_size

313772

1

T4

1

T5

24376

T30

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32877	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

710479

1

T1

1

T2

1

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	191793	1			T5	25512		T50	3872		T11	22756
values[0x0]	268319	1			T2	3		T3	2		T4	4
values[0x1]	283244	1			T1	1		T2	7		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

725585

1

T1

1

T2

1

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2948	1			T5	424		T50	50		T11	358
valid_sources[0x01]	2793	1			T5	381		T50	59		T175	1
valid_sources[0x02]	2803	1			T5	383		T16	1		T80	2
valid_sources[0x03]	3093	1			T5	402		T50	72		T175	1
valid_sources[0x04]	2901	1			T5	371		T50	62		T154	1
valid_sources[0x05]	2940	1			T5	401		T50	56		T11	351
valid_sources[0x06]	2857	1			T5	421		T74	1		T16	1
valid_sources[0x07]	2950	1			T5	415		T50	52		T11	389
valid_sources[0x08]	2929	1			T5	378		T80	2		T50	58
valid_sources[0x09]	2911	1			T5	385		T50	68		T176	2
valid_sources[0x0a]	2933	1			T5	357		T50	63		T11	379
valid_sources[0x0b]	2852	1			T5	390		T50	49		T76	5
valid_sources[0x0c]	2831	1			T4	2		T5	355		T50	53
valid_sources[0x0d]	3062	1			T5	434		T50	68		T17	1
valid_sources[0x0e]	2915	1			T5	389		T79	1		T50	47
valid_sources[0x0f]	2863	1			T5	398		T50	60		T11	372
valid_sources[0x10]	2849	1			T5	366		T50	62		T26	2
valid_sources[0x11]	2882	1			T5	417		T50	54		T11	328
valid_sources[0x12]	2835	1			T4	2		T5	410		T50	75
valid_sources[0x13]	2883	1			T5	341		T50	62		T44	1
valid_sources[0x14]	2789	1			T5	330		T50	55		T11	320
valid_sources[0x15]	2879	1			T5	382		T50	61		T33	2
valid_sources[0x16]	2875	1			T5	366		T50	68		T145	1
valid_sources[0x17]	2925	1			T5	394		T50	66		T11	353
valid_sources[0x18]	2991	1			T5	413		T50	52		T11	386
valid_sources[0x19]	2905	1			T5	440		T50	58		T177	1
valid_sources[0x1a]	2957	1			T5	409		T50	52		T178	6
valid_sources[0x1b]	2795	1			T5	400		T50	58		T11	321
valid_sources[0x1c]	2888	1			T5	363		T50	50		T11	352
valid_sources[0x1d]	2985	1			T5	345		T50	98		T174	1
valid_sources[0x1e]	2901	1			T5	433		T39	2		T80	4
valid_sources[0x1f]	2871	1			T5	370		T50	56		T179	1
valid_sources[0x20]	2921	1			T5	405		T50	71		T146	1
valid_sources[0x21]	2930	1			T5	396		T50	64		T11	345
valid_sources[0x22]	2831	1			T5	354		T50	65		T150	1
valid_sources[0x23]	2958	1			T5	406		T50	49		T149	4
valid_sources[0x24]	2956	1			T3	2		T5	394		T50	76
valid_sources[0x25]	2925	1			T5	379		T50	75		T97	1
valid_sources[0x26]	3025	1			T5	391		T56	1		T50	59
valid_sources[0x27]	2985	1			T5	406		T50	40		T11	438
valid_sources[0x28]	2802	1			T5	387		T50	63		T180	3
valid_sources[0x29]	3033	1			T5	379		T16	1		T50	57
valid_sources[0x2a]	2839	1			T5	398		T50	54		T62	1
valid_sources[0x2b]	3011	1			T5	378		T50	53		T11	409
valid_sources[0x2c]	2901	1			T5	360		T50	51		T181	1
valid_sources[0x2d]	2869	1			T5	363		T56	1		T50	73
valid_sources[0x2e]	2904	1			T5	431		T50	59		T11	339
valid_sources[0x2f]	2845	1			T5	391		T50	54		T144	1
valid_sources[0x30]	2920	1			T5	402		T56	1		T50	59
valid_sources[0x31]	2892	1			T5	360		T50	55		T182	1
valid_sources[0x32]	2878	1			T5	408		T14	3		T74	1
valid_sources[0x33]	2871	1			T5	357		T50	42		T123	1
valid_sources[0x34]	2847	1			T5	329		T50	50		T11	311
valid_sources[0x35]	3052	1			T5	384		T50	83		T18	1
valid_sources[0x36]	2816	1			T5	374		T50	58		T11	307
valid_sources[0x37]	2848	1			T5	367		T183	1		T50	58
valid_sources[0x38]	2923	1			T5	376		T50	76		T184	1
valid_sources[0x39]	2980	1			T5	399		T50	46		T185	2
valid_sources[0x3a]	2824	1			T5	382		T16	1		T28	1
valid_sources[0x3b]	2975	1			T5	436		T50	57		T186	1
valid_sources[0x3c]	2857	1			T5	395		T50	71		T187	2
valid_sources[0x3d]	2994	1			T4	4		T5	403		T39	1
valid_sources[0x3e]	2844	1			T5	368		T50	66		T188	1
valid_sources[0x3f]	2897	1			T5	374		T50	79		T186	1
valid_sources[0x40]	2856	1			T5	418		T50	70		T11	300
valid_sources[0x41]	2955	1			T5	360		T50	79		T188	1
valid_sources[0x42]	2922	1			T5	393		T39	2		T50	70
valid_sources[0x43]	2875	1			T5	377		T50	58		T11	400
valid_sources[0x44]	2905	1			T5	380		T50	53		T189	1
valid_sources[0x45]	2938	1			T5	447		T183	1		T50	90
valid_sources[0x46]	2910	1			T5	375		T50	52		T190	4
valid_sources[0x47]	2884	1			T5	360		T35	7		T50	54
valid_sources[0x48]	2861	1			T5	401		T50	52		T190	3
valid_sources[0x49]	2844	1			T5	407		T50	74		T191	2
valid_sources[0x4a]	2937	1			T5	443		T50	59		T188	1
valid_sources[0x4b]	2831	1			T5	377		T50	84		T175	1
valid_sources[0x4c]	2912	1			T5	317		T50	54		T11	272
valid_sources[0x4d]	2884	1			T5	390		T183	1		T50	48
valid_sources[0x4e]	2848	1			T5	340		T50	61		T34	1
valid_sources[0x4f]	3031	1			T5	411		T30	4		T50	75
valid_sources[0x50]	2878	1			T5	377		T50	45		T11	315
valid_sources[0x51]	2944	1			T5	347		T50	58		T154	2
valid_sources[0x52]	2814	1			T5	371		T50	78		T11	303
valid_sources[0x53]	3030	1			T5	420		T50	60		T10	1
valid_sources[0x54]	2982	1			T5	435		T50	59		T44	1
valid_sources[0x55]	2934	1			T5	418		T16	1		T50	44
valid_sources[0x56]	2914	1			T5	338		T50	72		T192	10
valid_sources[0x57]	2843	1			T5	367		T50	62		T11	360
valid_sources[0x58]	2877	1			T5	407		T50	53		T153	6
valid_sources[0x59]	2836	1			T5	382		T50	82		T144	1
valid_sources[0x5a]	2887	1			T5	372		T50	55		T11	397
valid_sources[0x5b]	2923	1			T5	394		T50	45		T11	313
valid_sources[0x5c]	3013	1			T5	424		T50	54		T11	395
valid_sources[0x5d]	2836	1			T5	350		T50	70		T11	333
valid_sources[0x5e]	2879	1			T5	362		T50	42		T188	1
valid_sources[0x5f]	2983	1			T5	397		T50	41		T40	1
valid_sources[0x60]	2841	1			T5	371		T16	1		T50	61
valid_sources[0x61]	2824	1			T5	340		T50	70		T11	330
valid_sources[0x62]	2977	1			T5	409		T50	64		T11	407
valid_sources[0x63]	2817	1			T5	390		T183	1		T50	75
valid_sources[0x64]	2958	1			T5	370		T50	55		T141	12
valid_sources[0x65]	2893	1			T5	386		T50	51		T175	1
valid_sources[0x66]	2814	1			T5	391		T183	1		T50	74
valid_sources[0x67]	2788	1			T5	335		T39	2		T50	59
valid_sources[0x68]	2875	1			T5	403		T56	1		T50	47
valid_sources[0x69]	2807	1			T5	360		T50	47		T146	3
valid_sources[0x6a]	3013	1			T5	386		T50	71		T146	1
valid_sources[0x6b]	2898	1			T5	417		T50	56		T32	1
valid_sources[0x6c]	3023	1			T5	403		T50	42		T11	392
valid_sources[0x6d]	2768	1			T5	362		T50	48		T9	2
valid_sources[0x6e]	2995	1			T5	406		T78	1		T50	52
valid_sources[0x6f]	2938	1			T5	354		T50	54		T11	398
valid_sources[0x70]	2950	1			T5	396		T183	1		T50	79
valid_sources[0x71]	2817	1			T5	383		T50	45		T177	1
valid_sources[0x72]	2811	1			T5	351		T73	3		T50	50
valid_sources[0x73]	2885	1			T5	377		T50	59		T192	8
valid_sources[0x74]	2887	1			T5	409		T50	49		T11	340
valid_sources[0x75]	2838	1			T5	425		T50	58		T11	311
valid_sources[0x76]	2915	1			T5	404		T50	29		T11	331
valid_sources[0x77]	3390	1			T5	385		T50	43		T193	1
valid_sources[0x78]	2813	1			T5	387		T50	46		T32	1
valid_sources[0x79]	2788	1			T5	379		T50	61		T194	1
valid_sources[0x7a]	2961	1			T5	413		T50	67		T190	2
valid_sources[0x7b]	2934	1			T5	389		T50	35		T11	330
valid_sources[0x7c]	2868	1			T5	420		T50	42		T11	279
valid_sources[0x7d]	2899	1			T5	353		T50	56		T44	1
valid_sources[0x7e]	3679	1			T5	336		T50	62		T11	347
valid_sources[0x7f]	2894	1			T5	404		T50	64		T11	357
valid_sources[0x80]	2692	1			T5	366		T50	55		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

179054

1

T5

24068

T50

3658

T11

21638

values[0x0]

all_enables

biggest_size

265399

1

T3

2

T4

4

T5

35727

values[0x1]

all_enables

biggest_size

266026

1

T1

1

T2

1

T3

2