SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 3886041 | 1 | T1 | 2 | T3 | 3 | T4 | 39 | ||||
auto[1] | 1342103 | 1 | T5 | 191579 | T50 | 26328 | T42 | 80 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 5227967 | 1 | T1 | 2 | T3 | 3 | T4 | 39 | ||||
values[1] | 12 | 1 | T83 | 2 | T84 | 2 | T160 | 1 | ||||
values[2] | 7 | 1 | T161 | 1 | T162 | 1 | T163 | 1 | ||||
values[3] | 97 | 1 | T83 | 5 | T84 | 3 | T124 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 5227942 | 1 | T1 | 2 | T3 | 3 | T4 | 39 | ||||
values[1] | 19 | 1 | T125 | 1 | T161 | 2 | T164 | 1 | ||||
values[2] | 5 | 1 | T84 | 1 | T125 | 1 | T164 | 1 | ||||
values[3] | 107 | 1 | T83 | 8 | T84 | 9 | T124 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 5227864 | 1 | T1 | 2 | T3 | 3 | T4 | 39 | ||||
auto[TlIntgErrCmd] | 78 | 1 | T83 | 4 | T84 | 4 | T124 | 5 | ||||
auto[TlIntgErrData] | 103 | 1 | T83 | 8 | T84 | 7 | T124 | 3 | ||||
auto[TlIntgErrBoth] | 99 | 1 | T83 | 8 | T84 | 9 | T124 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 2086825 | 0 | T1 | 1 | T2 | 10 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 2086646 | 1 | T1 | 1 | T2 | 10 | T3 | 4 | ||||
values[1] | 15 | 1 | T83 | 1 | T84 | 3 | T124 | 2 | ||||
values[2] | 3 | 1 | T165 | 1 | T166 | 1 | T167 | 1 | ||||
values[3] | 89 | 1 | T83 | 6 | T84 | 2 | T124 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 2086640 | 1 | T1 | 1 | T2 | 10 | T3 | 4 | ||||
values[1] | 12 | 1 | T84 | 1 | T124 | 1 | T125 | 1 | ||||
values[2] | 4 | 1 | T168 | 1 | T169 | 1 | T165 | 1 | ||||
values[3] | 88 | 1 | T83 | 7 | T84 | 5 | T124 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 2086545 | 1 | T1 | 1 | T2 | 10 | T3 | 4 | ||||
auto[TlIntgErrCmd] | 95 | 1 | T83 | 7 | T84 | 8 | T124 | 3 | ||||
auto[TlIntgErrData] | 101 | 1 | T83 | 10 | T84 | 8 | T124 | 3 | ||||
auto[TlIntgErrBoth] | 84 | 1 | T83 | 3 | T84 | 4 | T124 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |