Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4077961

1

T3

2

T4

31

T5

547236

full_word

1150183

1

T1

2

T3

1

T4

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5227864	1			T1	2		T3	3		T4	39
auto[TlIntgErrCmd]	78	1			T83	4		T84	4		T124	5
auto[TlIntgErrData]	103	1			T83	8		T84	7		T124	3
auto[TlIntgErrBoth]	99	1			T83	8		T84	9		T124	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

754694

1

T1

1

T3

1

T4

3

auto[1]

4473450

1

T1

1

T3

2

T4

36

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	334491	1			T3	1		T4	2		T5	20056
auto[TlIntgErrNone]	partial	auto[1]	3743215	1			T3	1		T4	29		T5	527180
auto[TlIntgErrNone]	full_word	auto[0]	420068	1			T1	1		T4	1		T5	18906
auto[TlIntgErrNone]	full_word	auto[1]	730090	1			T1	1		T3	1		T4	7
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T84	2		T124	5		T125	4
auto[TlIntgErrCmd]	partial	auto[1]	39	1			T83	4		T84	2		T125	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T161	1		T168	1		T166	2
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T166	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T83	2		T84	3		T124	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T83	5		T84	3		T124	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T84	1		T124	1		T168	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T83	1		T125	1		T168	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T83	4		T84	5		T125	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T83	4		T84	4		T124	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T166	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T125	1		T161	1		T160	1