Assert Coverage for Module :
rv_dm_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166596223 |
992790 |
0 |
0 |
T5 |
659623 |
140941 |
0 |
0 |
T6 |
6825 |
0 |
0 |
0 |
T11 |
0 |
114598 |
0 |
0 |
T13 |
493741 |
0 |
0 |
0 |
T30 |
363457 |
0 |
0 |
0 |
T36 |
11467 |
0 |
0 |
0 |
T37 |
4475 |
0 |
0 |
0 |
T38 |
44860 |
0 |
0 |
0 |
T39 |
8063 |
0 |
0 |
0 |
T50 |
0 |
20142 |
0 |
0 |
T56 |
9751 |
0 |
0 |
0 |
T59 |
0 |
50246 |
0 |
0 |
T60 |
0 |
63141 |
0 |
0 |
T61 |
0 |
284134 |
0 |
0 |
T73 |
7888 |
0 |
0 |
0 |
T81 |
0 |
257582 |
0 |
0 |
T82 |
0 |
470 |
0 |
0 |
T83 |
0 |
6 |
0 |
0 |
T84 |
0 |
4 |
0 |
0 |
late_debug_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166596223 |
51951 |
0 |
0 |
T11 |
672605 |
41260 |
0 |
0 |
T59 |
150460 |
0 |
0 |
0 |
T85 |
0 |
38 |
0 |
0 |
T87 |
0 |
238 |
0 |
0 |
T88 |
0 |
436 |
0 |
0 |
T89 |
0 |
5 |
0 |
0 |
T94 |
0 |
1 |
0 |
0 |
T112 |
0 |
2 |
0 |
0 |
T124 |
0 |
19 |
0 |
0 |
T125 |
0 |
38 |
0 |
0 |
T126 |
0 |
135 |
0 |
0 |
T127 |
11909 |
0 |
0 |
0 |
T128 |
898954 |
0 |
0 |
0 |
T129 |
319722 |
0 |
0 |
0 |
T130 |
111517 |
0 |
0 |
0 |
T131 |
179134 |
0 |
0 |
0 |
T132 |
358074 |
0 |
0 |
0 |
T133 |
1157 |
0 |
0 |
0 |
T134 |
4015 |
0 |
0 |
0 |
late_debug_enable_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166596223 |
45415 |
0 |
0 |
T11 |
672605 |
35476 |
0 |
0 |
T59 |
150460 |
0 |
0 |
0 |
T85 |
0 |
30 |
0 |
0 |
T87 |
0 |
216 |
0 |
0 |
T88 |
0 |
517 |
0 |
0 |
T89 |
0 |
3 |
0 |
0 |
T94 |
0 |
8 |
0 |
0 |
T95 |
0 |
1041 |
0 |
0 |
T112 |
0 |
4 |
0 |
0 |
T124 |
0 |
29 |
0 |
0 |
T125 |
0 |
23 |
0 |
0 |
T127 |
11909 |
0 |
0 |
0 |
T128 |
898954 |
0 |
0 |
0 |
T129 |
319722 |
0 |
0 |
0 |
T130 |
111517 |
0 |
0 |
0 |
T131 |
179134 |
0 |
0 |
0 |
T132 |
358074 |
0 |
0 |
0 |
T133 |
1157 |
0 |
0 |
0 |
T134 |
4015 |
0 |
0 |
0 |