Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80683380 |
80627019 |
0 |
0 |
T1 |
42530 |
42473 |
0 |
0 |
T2 |
3133 |
3048 |
0 |
0 |
T3 |
170702 |
170473 |
0 |
0 |
T4 |
573838 |
573486 |
0 |
0 |
T5 |
659623 |
659510 |
0 |
0 |
T6 |
6825 |
6772 |
0 |
0 |
T36 |
11467 |
11377 |
0 |
0 |
T37 |
4475 |
4421 |
0 |
0 |
T38 |
44860 |
43432 |
0 |
0 |
T39 |
8063 |
7985 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80683380 |
80627019 |
0 |
0 |
T1 |
42530 |
42473 |
0 |
0 |
T2 |
3133 |
3048 |
0 |
0 |
T3 |
170702 |
170473 |
0 |
0 |
T4 |
573838 |
573486 |
0 |
0 |
T5 |
659623 |
659510 |
0 |
0 |
T6 |
6825 |
6772 |
0 |
0 |
T36 |
11467 |
11377 |
0 |
0 |
T37 |
4475 |
4421 |
0 |
0 |
T38 |
44860 |
43432 |
0 |
0 |
T39 |
8063 |
7985 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80683380 |
80627019 |
0 |
0 |
T1 |
42530 |
42473 |
0 |
0 |
T2 |
3133 |
3048 |
0 |
0 |
T3 |
170702 |
170473 |
0 |
0 |
T4 |
573838 |
573486 |
0 |
0 |
T5 |
659623 |
659510 |
0 |
0 |
T6 |
6825 |
6772 |
0 |
0 |
T36 |
11467 |
11377 |
0 |
0 |
T37 |
4475 |
4421 |
0 |
0 |
T38 |
44860 |
43432 |
0 |
0 |
T39 |
8063 |
7985 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80683380 |
80627019 |
0 |
0 |
T1 |
42530 |
42473 |
0 |
0 |
T2 |
3133 |
3048 |
0 |
0 |
T3 |
170702 |
170473 |
0 |
0 |
T4 |
573838 |
573486 |
0 |
0 |
T5 |
659623 |
659510 |
0 |
0 |
T6 |
6825 |
6772 |
0 |
0 |
T36 |
11467 |
11377 |
0 |
0 |
T37 |
4475 |
4421 |
0 |
0 |
T38 |
44860 |
43432 |
0 |
0 |
T39 |
8063 |
7985 |
0 |
0 |