SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.09 | 100.00 | 88.89 | 85.71 | 95.83 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1470 | 1470 | 0 | 0 |
OutputsKnown_A | 484100280 | 483762114 | 0 | 0 |
gen_flops.OutputDelay_A | 242050140 | 241874379 | 0 | 2205 |
gen_no_flops.OutputDelay_A | 242050140 | 241881057 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1470 | 1470 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T36 | 6 | 6 | 0 | 0 |
T37 | 6 | 6 | 0 | 0 |
T38 | 6 | 6 | 0 | 0 |
T39 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 484100280 | 483762114 | 0 | 0 |
T1 | 255180 | 254838 | 0 | 0 |
T2 | 18798 | 18288 | 0 | 0 |
T3 | 1024212 | 1022838 | 0 | 0 |
T4 | 3443028 | 3440916 | 0 | 0 |
T5 | 3957738 | 3957060 | 0 | 0 |
T6 | 40950 | 40632 | 0 | 0 |
T36 | 68802 | 68262 | 0 | 0 |
T37 | 26850 | 26526 | 0 | 0 |
T38 | 269160 | 260592 | 0 | 0 |
T39 | 48378 | 47910 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 242050140 | 241874379 | 0 | 2205 |
T1 | 127590 | 127410 | 0 | 9 |
T2 | 9399 | 9135 | 0 | 9 |
T3 | 512106 | 511392 | 0 | 9 |
T4 | 1721514 | 1720413 | 0 | 9 |
T5 | 1978869 | 1978524 | 0 | 9 |
T6 | 20475 | 20307 | 0 | 9 |
T36 | 34401 | 34122 | 0 | 9 |
T37 | 13425 | 13254 | 0 | 9 |
T38 | 134580 | 130107 | 0 | 9 |
T39 | 24189 | 23946 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 242050140 | 241881057 | 0 | 0 |
T1 | 127590 | 127419 | 0 | 0 |
T2 | 9399 | 9144 | 0 | 0 |
T3 | 512106 | 511419 | 0 | 0 |
T4 | 1721514 | 1720458 | 0 | 0 |
T5 | 1978869 | 1978530 | 0 | 0 |
T6 | 20475 | 20316 | 0 | 0 |
T36 | 34401 | 34131 | 0 | 0 |
T37 | 13425 | 13263 | 0 | 0 |
T38 | 134580 | 130296 | 0 | 0 |
T39 | 24189 | 23955 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 80683380 | 80627019 | 0 | 0 |
gen_flops.OutputDelay_A | 80683380 | 80624793 | 0 | 735 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80627019 | 0 | 0 |
T1 | 42530 | 42473 | 0 | 0 |
T2 | 3133 | 3048 | 0 | 0 |
T3 | 170702 | 170473 | 0 | 0 |
T4 | 573838 | 573486 | 0 | 0 |
T5 | 659623 | 659510 | 0 | 0 |
T6 | 6825 | 6772 | 0 | 0 |
T36 | 11467 | 11377 | 0 | 0 |
T37 | 4475 | 4421 | 0 | 0 |
T38 | 44860 | 43432 | 0 | 0 |
T39 | 8063 | 7985 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80624793 | 0 | 735 |
T1 | 42530 | 42470 | 0 | 3 |
T2 | 3133 | 3045 | 0 | 3 |
T3 | 170702 | 170464 | 0 | 3 |
T4 | 573838 | 573471 | 0 | 3 |
T5 | 659623 | 659508 | 0 | 3 |
T6 | 6825 | 6769 | 0 | 3 |
T36 | 11467 | 11374 | 0 | 3 |
T37 | 4475 | 4418 | 0 | 3 |
T38 | 44860 | 43369 | 0 | 3 |
T39 | 8063 | 7982 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 80683380 | 80627019 | 0 | 0 |
gen_flops.OutputDelay_A | 80683380 | 80624793 | 0 | 735 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80627019 | 0 | 0 |
T1 | 42530 | 42473 | 0 | 0 |
T2 | 3133 | 3048 | 0 | 0 |
T3 | 170702 | 170473 | 0 | 0 |
T4 | 573838 | 573486 | 0 | 0 |
T5 | 659623 | 659510 | 0 | 0 |
T6 | 6825 | 6772 | 0 | 0 |
T36 | 11467 | 11377 | 0 | 0 |
T37 | 4475 | 4421 | 0 | 0 |
T38 | 44860 | 43432 | 0 | 0 |
T39 | 8063 | 7985 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80624793 | 0 | 735 |
T1 | 42530 | 42470 | 0 | 3 |
T2 | 3133 | 3045 | 0 | 3 |
T3 | 170702 | 170464 | 0 | 3 |
T4 | 573838 | 573471 | 0 | 3 |
T5 | 659623 | 659508 | 0 | 3 |
T6 | 6825 | 6769 | 0 | 3 |
T36 | 11467 | 11374 | 0 | 3 |
T37 | 4475 | 4418 | 0 | 3 |
T38 | 44860 | 43369 | 0 | 3 |
T39 | 8063 | 7982 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 80683380 | 80627019 | 0 | 0 |
gen_no_flops.OutputDelay_A | 80683380 | 80627019 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80627019 | 0 | 0 |
T1 | 42530 | 42473 | 0 | 0 |
T2 | 3133 | 3048 | 0 | 0 |
T3 | 170702 | 170473 | 0 | 0 |
T4 | 573838 | 573486 | 0 | 0 |
T5 | 659623 | 659510 | 0 | 0 |
T6 | 6825 | 6772 | 0 | 0 |
T36 | 11467 | 11377 | 0 | 0 |
T37 | 4475 | 4421 | 0 | 0 |
T38 | 44860 | 43432 | 0 | 0 |
T39 | 8063 | 7985 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80627019 | 0 | 0 |
T1 | 42530 | 42473 | 0 | 0 |
T2 | 3133 | 3048 | 0 | 0 |
T3 | 170702 | 170473 | 0 | 0 |
T4 | 573838 | 573486 | 0 | 0 |
T5 | 659623 | 659510 | 0 | 0 |
T6 | 6825 | 6772 | 0 | 0 |
T36 | 11467 | 11377 | 0 | 0 |
T37 | 4475 | 4421 | 0 | 0 |
T38 | 44860 | 43432 | 0 | 0 |
T39 | 8063 | 7985 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 80683380 | 80627019 | 0 | 0 |
gen_flops.OutputDelay_A | 80683380 | 80624793 | 0 | 735 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80627019 | 0 | 0 |
T1 | 42530 | 42473 | 0 | 0 |
T2 | 3133 | 3048 | 0 | 0 |
T3 | 170702 | 170473 | 0 | 0 |
T4 | 573838 | 573486 | 0 | 0 |
T5 | 659623 | 659510 | 0 | 0 |
T6 | 6825 | 6772 | 0 | 0 |
T36 | 11467 | 11377 | 0 | 0 |
T37 | 4475 | 4421 | 0 | 0 |
T38 | 44860 | 43432 | 0 | 0 |
T39 | 8063 | 7985 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80624793 | 0 | 735 |
T1 | 42530 | 42470 | 0 | 3 |
T2 | 3133 | 3045 | 0 | 3 |
T3 | 170702 | 170464 | 0 | 3 |
T4 | 573838 | 573471 | 0 | 3 |
T5 | 659623 | 659508 | 0 | 3 |
T6 | 6825 | 6769 | 0 | 3 |
T36 | 11467 | 11374 | 0 | 3 |
T37 | 4475 | 4418 | 0 | 3 |
T38 | 44860 | 43369 | 0 | 3 |
T39 | 8063 | 7982 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 80683380 | 80627019 | 0 | 0 |
gen_no_flops.OutputDelay_A | 80683380 | 80627019 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80627019 | 0 | 0 |
T1 | 42530 | 42473 | 0 | 0 |
T2 | 3133 | 3048 | 0 | 0 |
T3 | 170702 | 170473 | 0 | 0 |
T4 | 573838 | 573486 | 0 | 0 |
T5 | 659623 | 659510 | 0 | 0 |
T6 | 6825 | 6772 | 0 | 0 |
T36 | 11467 | 11377 | 0 | 0 |
T37 | 4475 | 4421 | 0 | 0 |
T38 | 44860 | 43432 | 0 | 0 |
T39 | 8063 | 7985 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80627019 | 0 | 0 |
T1 | 42530 | 42473 | 0 | 0 |
T2 | 3133 | 3048 | 0 | 0 |
T3 | 170702 | 170473 | 0 | 0 |
T4 | 573838 | 573486 | 0 | 0 |
T5 | 659623 | 659510 | 0 | 0 |
T6 | 6825 | 6772 | 0 | 0 |
T36 | 11467 | 11377 | 0 | 0 |
T37 | 4475 | 4421 | 0 | 0 |
T38 | 44860 | 43432 | 0 | 0 |
T39 | 8063 | 7985 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 80683380 | 80627019 | 0 | 0 |
gen_no_flops.OutputDelay_A | 80683380 | 80627019 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80627019 | 0 | 0 |
T1 | 42530 | 42473 | 0 | 0 |
T2 | 3133 | 3048 | 0 | 0 |
T3 | 170702 | 170473 | 0 | 0 |
T4 | 573838 | 573486 | 0 | 0 |
T5 | 659623 | 659510 | 0 | 0 |
T6 | 6825 | 6772 | 0 | 0 |
T36 | 11467 | 11377 | 0 | 0 |
T37 | 4475 | 4421 | 0 | 0 |
T38 | 44860 | 43432 | 0 | 0 |
T39 | 8063 | 7985 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80683380 | 80627019 | 0 | 0 |
T1 | 42530 | 42473 | 0 | 0 |
T2 | 3133 | 3048 | 0 | 0 |
T3 | 170702 | 170473 | 0 | 0 |
T4 | 573838 | 573486 | 0 | 0 |
T5 | 659623 | 659510 | 0 | 0 |
T6 | 6825 | 6772 | 0 | 0 |
T36 | 11467 | 11377 | 0 | 0 |
T37 | 4475 | 4421 | 0 | 0 |
T38 | 44860 | 43432 | 0 | 0 |
T39 | 8063 | 7985 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |