Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	706052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1006376

1

T2

2

T7

8

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	631018	1			T7	2		T9	1		T4	6
values[0x0]	343195	1			T2	2		T7	5		T4	15
values[0x1]	738215	1			T2	7		T7	11		T8	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	342387	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1370041

1

T2

2

T7

9

T8

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7098	1			T5	958		T6	167		T79	1
valid_sources[0x01]	6040	1			T5	962		T6	154		T79	1
valid_sources[0x02]	6465	1			T5	1044		T6	170		T13	2
valid_sources[0x03]	6444	1			T5	866		T6	172		T37	140
valid_sources[0x04]	6976	1			T5	906		T6	158		T78	1
valid_sources[0x05]	7106	1			T5	980		T6	183		T37	175
valid_sources[0x06]	6431	1			T5	937		T6	159		T37	160
valid_sources[0x07]	6903	1			T5	899		T6	148		T37	161
valid_sources[0x08]	6974	1			T5	961		T6	168		T37	163
valid_sources[0x09]	6185	1			T5	975		T6	172		T78	1
valid_sources[0x0a]	6458	1			T5	953		T6	176		T34	1
valid_sources[0x0b]	6189	1			T9	2		T5	924		T6	153
valid_sources[0x0c]	6810	1			T5	867		T6	171		T37	151
valid_sources[0x0d]	6656	1			T5	999		T6	172		T37	128
valid_sources[0x0e]	6154	1			T5	994		T6	193		T37	179
valid_sources[0x0f]	6091	1			T5	973		T6	168		T37	154
valid_sources[0x10]	6346	1			T8	1		T5	931		T6	150
valid_sources[0x11]	6361	1			T5	1038		T6	159		T37	145
valid_sources[0x12]	7058	1			T2	1		T5	913		T6	134
valid_sources[0x13]	6502	1			T5	881		T6	172		T79	1
valid_sources[0x14]	6102	1			T8	1		T5	945		T6	171
valid_sources[0x15]	6163	1			T5	843		T6	169		T37	169
valid_sources[0x16]	6373	1			T5	876		T6	175		T78	1
valid_sources[0x17]	6392	1			T5	1036		T6	171		T37	159
valid_sources[0x18]	6677	1			T2	1		T5	916		T6	152
valid_sources[0x19]	6771	1			T5	881		T6	153		T37	166
valid_sources[0x1a]	6887	1			T5	915		T6	161		T79	1
valid_sources[0x1b]	7677	1			T5	961		T6	179		T33	4
valid_sources[0x1c]	6279	1			T5	883		T6	149		T37	146
valid_sources[0x1d]	6177	1			T5	918		T38	2		T6	163
valid_sources[0x1e]	7517	1			T5	943		T6	153		T37	130
valid_sources[0x1f]	7304	1			T5	950		T6	190		T20	3
valid_sources[0x20]	6353	1			T5	993		T6	164		T37	162
valid_sources[0x21]	6304	1			T5	871		T6	149		T37	158
valid_sources[0x22]	6818	1			T5	1071		T6	163		T37	151
valid_sources[0x23]	6431	1			T5	815		T6	178		T37	165
valid_sources[0x24]	6885	1			T5	841		T6	171		T37	155
valid_sources[0x25]	7032	1			T5	950		T6	144		T37	165
valid_sources[0x26]	6883	1			T5	856		T6	167		T37	151
valid_sources[0x27]	6131	1			T5	894		T6	161		T37	138
valid_sources[0x28]	6697	1			T5	918		T6	154		T34	1
valid_sources[0x29]	6637	1			T5	943		T6	155		T37	195
valid_sources[0x2a]	6995	1			T5	918		T6	147		T37	152
valid_sources[0x2b]	6346	1			T5	968		T6	184		T37	162
valid_sources[0x2c]	6760	1			T5	967		T6	158		T79	1
valid_sources[0x2d]	6699	1			T5	834		T6	176		T37	150
valid_sources[0x2e]	7893	1			T5	994		T6	190		T37	126
valid_sources[0x2f]	7093	1			T5	884		T6	138		T37	155
valid_sources[0x30]	7781	1			T5	1004		T6	168		T37	167
valid_sources[0x31]	7609	1			T5	927		T6	169		T37	167
valid_sources[0x32]	6759	1			T5	907		T6	156		T37	169
valid_sources[0x33]	6753	1			T5	851		T6	166		T37	149
valid_sources[0x34]	6544	1			T5	973		T6	155		T37	137
valid_sources[0x35]	6184	1			T5	854		T6	151		T37	175
valid_sources[0x36]	6477	1			T5	1005		T6	179		T79	1
valid_sources[0x37]	6950	1			T5	1037		T6	193		T37	156
valid_sources[0x38]	6995	1			T5	982		T6	182		T37	155
valid_sources[0x39]	6319	1			T5	886		T6	188		T37	149
valid_sources[0x3a]	6251	1			T5	947		T6	166		T37	171
valid_sources[0x3b]	7003	1			T5	917		T6	168		T21	2
valid_sources[0x3c]	6495	1			T5	1003		T6	171		T20	3
valid_sources[0x3d]	6486	1			T5	950		T6	198		T79	1
valid_sources[0x3e]	8101	1			T5	978		T6	197		T34	1
valid_sources[0x3f]	6818	1			T5	928		T6	170		T79	1
valid_sources[0x40]	6424	1			T5	913		T6	151		T37	167
valid_sources[0x41]	6951	1			T5	894		T6	157		T79	1
valid_sources[0x42]	5996	1			T5	1046		T6	177		T37	145
valid_sources[0x43]	6437	1			T5	853		T6	163		T37	162
valid_sources[0x44]	7353	1			T5	964		T6	186		T37	179
valid_sources[0x45]	6533	1			T2	1		T5	985		T6	150
valid_sources[0x46]	6060	1			T5	850		T6	162		T37	139
valid_sources[0x47]	7129	1			T5	924		T6	165		T37	145
valid_sources[0x48]	6485	1			T5	962		T6	180		T37	168
valid_sources[0x49]	6835	1			T5	942		T6	185		T37	150
valid_sources[0x4a]	6921	1			T5	1004		T6	174		T33	1
valid_sources[0x4b]	7702	1			T5	921		T6	174		T37	127
valid_sources[0x4c]	6777	1			T2	4		T5	996		T6	142
valid_sources[0x4d]	6691	1			T5	958		T6	149		T73	1
valid_sources[0x4e]	6235	1			T5	1024		T6	160		T37	183
valid_sources[0x4f]	7153	1			T5	987		T6	166		T78	1
valid_sources[0x50]	7022	1			T5	886		T6	133		T37	151
valid_sources[0x51]	6157	1			T5	952		T6	167		T79	1
valid_sources[0x52]	7434	1			T5	894		T6	169		T37	134
valid_sources[0x53]	6542	1			T5	913		T6	169		T37	182
valid_sources[0x54]	7718	1			T5	855		T6	163		T37	136
valid_sources[0x55]	7081	1			T5	978		T6	152		T37	136
valid_sources[0x56]	6699	1			T5	959		T6	161		T37	167
valid_sources[0x57]	7761	1			T5	929		T6	157		T37	153
valid_sources[0x58]	6991	1			T5	920		T6	157		T37	147
valid_sources[0x59]	6939	1			T5	1016		T6	151		T37	164
valid_sources[0x5a]	6922	1			T5	947		T6	154		T79	3
valid_sources[0x5b]	6506	1			T5	971		T6	161		T79	1
valid_sources[0x5c]	6964	1			T2	1		T5	922		T6	163
valid_sources[0x5d]	6922	1			T5	923		T6	168		T37	136
valid_sources[0x5e]	6412	1			T5	825		T6	151		T37	138
valid_sources[0x5f]	7245	1			T5	919		T6	167		T78	3
valid_sources[0x60]	6970	1			T5	868		T6	162		T37	155
valid_sources[0x61]	6437	1			T5	923		T6	166		T37	163
valid_sources[0x62]	6432	1			T5	972		T6	170		T37	156
valid_sources[0x63]	6323	1			T5	883		T6	150		T79	1
valid_sources[0x64]	6684	1			T5	932		T6	144		T37	159
valid_sources[0x65]	6647	1			T5	906		T6	186		T33	1
valid_sources[0x66]	6642	1			T5	975		T6	173		T20	3
valid_sources[0x67]	7365	1			T5	898		T6	178		T37	168
valid_sources[0x68]	6004	1			T5	901		T6	170		T78	1
valid_sources[0x69]	7190	1			T5	1020		T6	148		T79	2
valid_sources[0x6a]	6634	1			T5	944		T6	167		T79	1
valid_sources[0x6b]	5830	1			T5	882		T6	173		T37	117
valid_sources[0x6c]	6333	1			T5	987		T6	172		T79	1
valid_sources[0x6d]	6558	1			T5	985		T6	178		T78	2
valid_sources[0x6e]	6533	1			T5	893		T38	1		T6	169
valid_sources[0x6f]	6238	1			T5	962		T6	150		T37	139
valid_sources[0x70]	6806	1			T7	5		T5	961		T6	184
valid_sources[0x71]	6233	1			T5	867		T6	161		T33	1
valid_sources[0x72]	6483	1			T5	923		T6	125		T78	1
valid_sources[0x73]	6247	1			T5	927		T6	171		T20	1
valid_sources[0x74]	6497	1			T5	893		T6	172		T37	192
valid_sources[0x75]	5755	1			T5	952		T6	162		T37	143
valid_sources[0x76]	6884	1			T5	1007		T6	173		T37	193
valid_sources[0x77]	6916	1			T5	912		T6	161		T37	151
valid_sources[0x78]	6201	1			T5	891		T6	157		T79	1
valid_sources[0x79]	6953	1			T5	929		T6	181		T37	157
valid_sources[0x7a]	6993	1			T5	1008		T6	181		T37	167
valid_sources[0x7b]	6553	1			T5	960		T6	187		T78	1
valid_sources[0x7c]	6219	1			T5	797		T6	162		T79	1
valid_sources[0x7d]	6755	1			T5	929		T6	164		T79	1
valid_sources[0x7e]	7253	1			T5	1028		T6	156		T37	161
valid_sources[0x7f]	6272	1			T5	989		T6	169		T37	159
valid_sources[0x80]	6364	1			T5	831		T6	168		T20	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

410357

1

T7

1

T4

3

T5

28593

values[0x0]

all_enables

biggest_size

298746

1

T2

1

T7

4

T4

5

values[0x1]

all_enables

biggest_size

297273

1

T2

1

T7

3

T8

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30494	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

645393

1

T1

11

T2

7

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	175238	1			T5	42821		T6	8004		T37	6970
values[0x0]	243600	1			T1	5		T2	6		T3	3
values[0x1]	257049	1			T1	6		T2	1		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

659305

1

T1

11

T2

7

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2699	1			T5	555		T6	115		T77	1
valid_sources[0x01]	2371	1			T3	1		T5	699		T6	97
valid_sources[0x02]	2578	1			T61	1		T5	676		T6	118
valid_sources[0x03]	2642	1			T5	686		T6	127		T37	107
valid_sources[0x04]	2941	1			T5	705		T6	138		T60	1
valid_sources[0x05]	2276	1			T5	596		T6	138		T73	1
valid_sources[0x06]	2466	1			T5	703		T6	98		T37	111
valid_sources[0x07]	2449	1			T5	752		T6	102		T37	114
valid_sources[0x08]	2715	1			T5	601		T6	119		T37	99
valid_sources[0x09]	2777	1			T5	576		T6	139		T26	2
valid_sources[0x0a]	3009	1			T61	1		T5	735		T6	138
valid_sources[0x0b]	2130	1			T5	695		T6	147		T131	1
valid_sources[0x0c]	3520	1			T5	753		T6	87		T37	103
valid_sources[0x0d]	2767	1			T5	622		T6	136		T37	83
valid_sources[0x0e]	2659	1			T5	643		T6	112		T21	4
valid_sources[0x0f]	2700	1			T5	647		T6	125		T37	85
valid_sources[0x10]	2829	1			T5	811		T6	111		T37	102
valid_sources[0x11]	2596	1			T5	719		T6	147		T37	95
valid_sources[0x12]	2409	1			T5	546		T6	113		T37	110
valid_sources[0x13]	2572	1			T5	617		T6	131		T37	110
valid_sources[0x14]	2575	1			T5	703		T6	109		T37	148
valid_sources[0x15]	2393	1			T16	2		T5	697		T6	137
valid_sources[0x16]	2937	1			T61	1		T5	811		T6	123
valid_sources[0x17]	2740	1			T24	1		T5	635		T6	117
valid_sources[0x18]	2431	1			T5	622		T6	103		T37	101
valid_sources[0x19]	3040	1			T5	505		T6	113		T37	113
valid_sources[0x1a]	2560	1			T5	642		T6	149		T37	91
valid_sources[0x1b]	2687	1			T5	633		T6	116		T37	103
valid_sources[0x1c]	2484	1			T5	596		T6	157		T73	1
valid_sources[0x1d]	2969	1			T5	679		T6	137		T37	103
valid_sources[0x1e]	2558	1			T7	1		T5	817		T6	119
valid_sources[0x1f]	2291	1			T5	449		T6	99		T37	92
valid_sources[0x20]	2375	1			T5	627		T6	94		T37	108
valid_sources[0x21]	2338	1			T5	596		T6	132		T37	96
valid_sources[0x22]	2480	1			T5	572		T6	132		T162	1
valid_sources[0x23]	2519	1			T5	587		T6	98		T37	104
valid_sources[0x24]	3347	1			T5	745		T6	142		T37	113
valid_sources[0x25]	2922	1			T5	713		T6	148		T37	112
valid_sources[0x26]	2969	1			T5	810		T6	112		T37	95
valid_sources[0x27]	2695	1			T5	645		T6	158		T37	86
valid_sources[0x28]	3006	1			T61	1		T5	652		T6	130
valid_sources[0x29]	2556	1			T5	582		T6	119		T37	75
valid_sources[0x2a]	2670	1			T5	562		T6	115		T37	92
valid_sources[0x2b]	2742	1			T5	496		T6	146		T37	70
valid_sources[0x2c]	2441	1			T5	838		T6	122		T37	112
valid_sources[0x2d]	2485	1			T61	1		T5	714		T6	111
valid_sources[0x2e]	2793	1			T5	593		T6	140		T37	135
valid_sources[0x2f]	2704	1			T5	665		T38	1		T6	111
valid_sources[0x30]	2397	1			T5	659		T6	158		T37	141
valid_sources[0x31]	2443	1			T5	549		T6	141		T37	131
valid_sources[0x32]	2848	1			T5	460		T6	112		T37	107
valid_sources[0x33]	2891	1			T5	825		T6	106		T21	1
valid_sources[0x34]	2988	1			T5	734		T6	126		T77	1
valid_sources[0x35]	2586	1			T5	779		T6	95		T37	102
valid_sources[0x36]	2565	1			T4	4		T5	732		T6	126
valid_sources[0x37]	2542	1			T5	512		T6	139		T53	1
valid_sources[0x38]	2655	1			T7	1		T8	1		T5	696
valid_sources[0x39]	2452	1			T5	638		T6	124		T37	78
valid_sources[0x3a]	2828	1			T5	681		T6	102		T77	1
valid_sources[0x3b]	2805	1			T5	611		T6	118		T37	92
valid_sources[0x3c]	2416	1			T5	713		T6	132		T37	79
valid_sources[0x3d]	2252	1			T5	675		T6	115		T37	105
valid_sources[0x3e]	2687	1			T5	638		T6	161		T37	135
valid_sources[0x3f]	2833	1			T5	596		T6	104		T37	84
valid_sources[0x40]	2652	1			T5	822		T6	115		T37	104
valid_sources[0x41]	2251	1			T5	638		T6	136		T37	108
valid_sources[0x42]	3297	1			T5	829		T6	108		T37	96
valid_sources[0x43]	3253	1			T5	791		T6	144		T163	1
valid_sources[0x44]	2168	1			T5	611		T6	135		T37	112
valid_sources[0x45]	3514	1			T61	1		T5	777		T6	159
valid_sources[0x46]	2403	1			T7	2		T5	694		T6	123
valid_sources[0x47]	2669	1			T5	685		T6	111		T37	92
valid_sources[0x48]	2725	1			T5	679		T6	114		T37	124
valid_sources[0x49]	2719	1			T27	1		T5	615		T6	114
valid_sources[0x4a]	2431	1			T5	461		T6	130		T37	126
valid_sources[0x4b]	2631	1			T5	576		T6	135		T37	91
valid_sources[0x4c]	2587	1			T5	695		T6	112		T37	109
valid_sources[0x4d]	3472	1			T5	808		T6	142		T37	97
valid_sources[0x4e]	2067	1			T7	1		T5	508		T6	80
valid_sources[0x4f]	2111	1			T5	599		T6	115		T37	102
valid_sources[0x50]	2723	1			T5	696		T6	118		T37	103
valid_sources[0x51]	2577	1			T5	783		T6	95		T37	100
valid_sources[0x52]	2881	1			T5	700		T6	142		T78	2
valid_sources[0x53]	2475	1			T5	488		T6	125		T73	1
valid_sources[0x54]	2729	1			T5	752		T6	140		T37	91
valid_sources[0x55]	2680	1			T5	671		T6	154		T77	1
valid_sources[0x56]	2816	1			T5	801		T6	99		T37	123
valid_sources[0x57]	2530	1			T5	574		T6	134		T37	151
valid_sources[0x58]	2290	1			T5	613		T6	98		T37	127
valid_sources[0x59]	2754	1			T5	687		T6	117		T37	95
valid_sources[0x5a]	3127	1			T5	679		T6	118		T37	89
valid_sources[0x5b]	2917	1			T4	3		T42	3		T5	686
valid_sources[0x5c]	2668	1			T2	4		T5	796		T6	99
valid_sources[0x5d]	2949	1			T5	722		T6	105		T37	84
valid_sources[0x5e]	2729	1			T5	719		T6	99		T37	105
valid_sources[0x5f]	2466	1			T5	715		T6	116		T37	85
valid_sources[0x60]	2472	1			T61	1		T5	663		T6	110
valid_sources[0x61]	2985	1			T5	764		T6	108		T37	130
valid_sources[0x62]	2160	1			T5	661		T6	155		T20	1
valid_sources[0x63]	2598	1			T5	838		T6	115		T37	79
valid_sources[0x64]	3080	1			T1	11		T5	788		T6	142
valid_sources[0x65]	3213	1			T5	926		T6	119		T48	4
valid_sources[0x66]	1962	1			T46	3		T5	599		T6	112
valid_sources[0x67]	2591	1			T5	694		T6	127		T37	94
valid_sources[0x68]	3288	1			T5	569		T6	123		T13	1
valid_sources[0x69]	2508	1			T5	742		T6	127		T37	132
valid_sources[0x6a]	2488	1			T5	718		T6	163		T26	1
valid_sources[0x6b]	2803	1			T5	771		T6	153		T37	99
valid_sources[0x6c]	2423	1			T5	695		T6	138		T37	113
valid_sources[0x6d]	2062	1			T5	494		T6	141		T91	1
valid_sources[0x6e]	2522	1			T7	1		T5	625		T6	104
valid_sources[0x6f]	2467	1			T5	644		T6	145		T37	111
valid_sources[0x70]	2181	1			T28	1		T5	643		T6	121
valid_sources[0x71]	1988	1			T5	569		T6	149		T37	110
valid_sources[0x72]	3344	1			T5	714		T6	99		T164	1
valid_sources[0x73]	2891	1			T5	632		T6	113		T77	1
valid_sources[0x74]	2861	1			T5	825		T6	127		T37	128
valid_sources[0x75]	2772	1			T5	634		T6	97		T37	123
valid_sources[0x76]	2423	1			T5	632		T6	118		T37	106
valid_sources[0x77]	3356	1			T3	1		T5	576		T6	117
valid_sources[0x78]	2439	1			T3	2		T5	818		T6	91
valid_sources[0x79]	2537	1			T61	1		T5	676		T6	114
valid_sources[0x7a]	2192	1			T5	461		T6	135		T37	105
valid_sources[0x7b]	2635	1			T5	883		T6	120		T37	113
valid_sources[0x7c]	2657	1			T5	532		T6	112		T37	121
valid_sources[0x7d]	3376	1			T5	736		T6	98		T37	95
valid_sources[0x7e]	2749	1			T5	538		T6	126		T37	118
valid_sources[0x7f]	2819	1			T5	516		T6	91		T37	125
valid_sources[0x80]	2595	1			T2	2		T5	670		T6	95

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

163389

1

T5

40460

T6

7556

T37

6591

values[0x0]

all_enables

biggest_size

240851

1

T1

5

T2

6

T3

1

values[0x1]

all_enables

biggest_size

241153

1

T1

6

T2

1

T3

1