SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 3670863 | 1 | T2 | 9 | T7 | 18 | T8 | 2 | ||||
auto[1] | 1228240 | 1 | T5 | 322453 | T6 | 61119 | T37 | 50567 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4898925 | 1 | T2 | 9 | T7 | 18 | T8 | 2 | ||||
values[1] | 15 | 1 | T130 | 1 | T116 | 1 | T117 | 1 | ||||
values[2] | 7 | 1 | T130 | 1 | T150 | 1 | T151 | 1 | ||||
values[3] | 100 | 1 | T129 | 7 | T130 | 3 | T116 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4898923 | 1 | T2 | 9 | T7 | 18 | T8 | 2 | ||||
values[1] | 18 | 1 | T129 | 2 | T116 | 1 | T150 | 1 | ||||
values[2] | 8 | 1 | T129 | 2 | T117 | 1 | T150 | 1 | ||||
values[3] | 100 | 1 | T129 | 8 | T130 | 3 | T116 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4898833 | 1 | T2 | 9 | T7 | 18 | T8 | 2 | ||||
auto[TlIntgErrCmd] | 90 | 1 | T129 | 4 | T130 | 5 | T116 | 1 | ||||
auto[TlIntgErrData] | 92 | 1 | T129 | 10 | T130 | 3 | T116 | 5 | ||||
auto[TlIntgErrBoth] | 88 | 1 | T129 | 6 | T130 | 2 | T116 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 1900756 | 0 | T1 | 11 | T2 | 7 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1900578 | 1 | T1 | 11 | T2 | 7 | T3 | 6 | ||||
values[1] | 25 | 1 | T129 | 2 | T130 | 2 | T150 | 2 | ||||
values[2] | 2 | 1 | T129 | 1 | T117 | 1 | - | - | ||||
values[3] | 98 | 1 | T129 | 9 | T130 | 2 | T116 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1900578 | 1 | T1 | 11 | T2 | 7 | T3 | 6 | ||||
values[1] | 28 | 1 | T130 | 1 | T116 | 1 | T117 | 3 | ||||
values[2] | 2 | 1 | T152 | 2 | - | - | - | - | ||||
values[3] | 78 | 1 | T129 | 9 | T130 | 2 | T116 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1900486 | 1 | T1 | 11 | T2 | 7 | T3 | 6 | ||||
auto[TlIntgErrCmd] | 92 | 1 | T129 | 7 | T130 | 3 | T116 | 6 | ||||
auto[TlIntgErrData] | 92 | 1 | T129 | 5 | T130 | 5 | T116 | 2 | ||||
auto[TlIntgErrBoth] | 86 | 1 | T129 | 8 | T130 | 2 | T116 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |