Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
3785167 |
1 |
|
|
T2 |
7 |
|
T7 |
10 |
|
T8 |
1 |
full_word |
1113936 |
1 |
|
|
T2 |
2 |
|
T7 |
8 |
|
T8 |
1 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
4898833 |
1 |
|
|
T2 |
9 |
|
T7 |
18 |
|
T8 |
2 |
auto[TlIntgErrCmd] |
90 |
1 |
|
|
T129 |
4 |
|
T130 |
5 |
|
T116 |
1 |
auto[TlIntgErrData] |
92 |
1 |
|
|
T129 |
10 |
|
T130 |
3 |
|
T116 |
5 |
auto[TlIntgErrBoth] |
88 |
1 |
|
|
T129 |
6 |
|
T130 |
2 |
|
T116 |
4 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
759749 |
1 |
|
|
T7 |
2 |
|
T9 |
1 |
|
T4 |
6 |
auto[1] |
4139354 |
1 |
|
|
T2 |
9 |
|
T7 |
16 |
|
T8 |
2 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
336217 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T4 |
3 |
auto[TlIntgErrNone] |
partial |
auto[1] |
3448708 |
1 |
|
|
T2 |
7 |
|
T7 |
9 |
|
T8 |
1 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
423400 |
1 |
|
|
T7 |
1 |
|
T4 |
3 |
|
T5 |
32001 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
690508 |
1 |
|
|
T2 |
2 |
|
T7 |
7 |
|
T8 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
42 |
1 |
|
|
T129 |
3 |
|
T130 |
2 |
|
T116 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
37 |
1 |
|
|
T129 |
1 |
|
T130 |
1 |
|
T117 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
5 |
1 |
|
|
T130 |
1 |
|
T117 |
1 |
|
T153 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
6 |
1 |
|
|
T130 |
1 |
|
T117 |
2 |
|
T154 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
40 |
1 |
|
|
T129 |
5 |
|
T130 |
1 |
|
T116 |
1 |
auto[TlIntgErrData] |
partial |
auto[1] |
44 |
1 |
|
|
T129 |
3 |
|
T130 |
2 |
|
T116 |
3 |
auto[TlIntgErrData] |
full_word |
auto[0] |
7 |
1 |
|
|
T129 |
1 |
|
T116 |
1 |
|
T155 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
1 |
1 |
|
|
T129 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrBoth] |
partial |
auto[0] |
33 |
1 |
|
|
T129 |
2 |
|
T130 |
1 |
|
T116 |
3 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
46 |
1 |
|
|
T129 |
3 |
|
T116 |
1 |
|
T117 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
5 |
1 |
|
|
T129 |
1 |
|
T150 |
2 |
|
T156 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
4 |
1 |
|
|
T130 |
1 |
|
T157 |
1 |
|
T158 |
1 |