Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	212546643	903527	0	0
late_debug_enable_rd_A	212546643	84150	0	0
late_debug_enable_regwen_rd_A	212546643	74135	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212546643	903527	0	0
T5	112865	235279	0	0
T6	133119	42223	0	0
T11	0	219615	0	0
T20	114802	0	0	0
T23	0	109731	0	0
T37	0	37864	0	0
T38	5738	0	0	0
T39	0	92938	0	0
T47	30867	0	0	0
T48	122552	0	0	0
T49	0	35690	0	0
T53	308784	0	0	0
T60	127908	0	0	0
T73	112533	0	0	0
T74	0	11650	0	0
T75	0	88480	0	0
T76	0	90	0	0
T77	1760	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212546643	84150	0	0
T23	0	37009	0	0
T35	192736	0	0	0
T37	194431	6413	0	0
T39	0	31636	0	0
T74	0	4546	0	0
T87	0	50	0	0
T116	0	43	0	0
T117	0	34	0	0
T118	0	25	0	0
T119	0	68	0	0
T120	0	88	0	0
T121	30346	0	0	0
T122	188880	0	0	0
T123	2038	0	0	0
T124	132879	0	0	0
T125	785939	0	0	0
T126	79083	0	0	0
T127	152389	0	0	0
T128	36678	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212546643	74135	0	0
T23	0	31947	0	0
T35	192736	0	0	0
T37	194431	5588	0	0
T39	0	27693	0	0
T74	0	4184	0	0
T87	0	27	0	0
T116	0	34	0	0
T117	0	25	0	0
T118	0	55	0	0
T119	0	49	0	0
T120	0	75	0	0
T121	30346	0	0	0
T122	188880	0	0	0
T123	2038	0	0	0
T124	132879	0	0	0
T125	785939	0	0	0
T126	79083	0	0	0
T127	152389	0	0	0
T128	36678	0	0	0