Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 34743299 34741871 0 0
selKnown1 138619691 138618263 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 34743299 34741871 0 0
T1 41994 41990 0 0
T2 23462 23458 0 0
T3 331 327 0 0
T4 21885 21881 0 0
T5 0 32 0 0
T6 0 16 0 0
T7 17463 17459 0 0
T8 2182 2178 0 0
T9 1719 1715 0 0
T15 32438 32434 0 0
T16 0 6 0 0
T27 1539 1535 0 0
T28 321 317 0 0
T46 0 4 0 0
T47 0 2 0 0
T48 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 138619691 138618263 0 0
T1 508540 508536 0 0
T2 181117 181113 0 0
T3 5816 5812 0 0
T4 499774 499770 0 0
T5 0 18 0 0
T6 0 10 0 0
T7 430049 430045 0 0
T8 8004 8000 0 0
T9 20662 20658 0 0
T15 425985 425981 0 0
T16 0 6 0 0
T20 0 6 0 0
T27 23124 23120 0 0
T28 6264 6260 0 0
T46 0 4 0 0
T48 0 6 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 15509750 15509503 0 0
selKnown1 119386541 119386294 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 15509750 15509503 0 0
T1 20986 20985 0 0
T2 11724 11723 0 0
T3 164 163 0 0
T4 10939 10938 0 0
T7 8729 8728 0 0
T8 1090 1089 0 0
T9 858 857 0 0
T15 16218 16217 0 0
T27 768 767 0 0
T28 159 158 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 119386541 119386294 0 0
T1 487532 487531 0 0
T2 169381 169380 0 0
T3 5650 5649 0 0
T4 488829 488828 0 0
T7 421316 421315 0 0
T8 6912 6911 0 0
T9 19802 19801 0 0
T15 409765 409764 0 0
T27 22354 22353 0 0
T28 6103 6102 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 761 514 0 0
selKnown1 695 448 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 761 514 0 0
T1 11 10 0 0
T2 7 6 0 0
T3 1 0 0 0
T4 3 2 0 0
T5 0 15 0 0
T6 0 8 0 0
T7 2 1 0 0
T8 1 0 0 0
T9 1 0 0 0
T15 1 0 0 0
T16 0 3 0 0
T27 1 0 0 0
T28 1 0 0 0
T46 0 2 0 0
T47 0 1 0 0
T48 0 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 695 448 0 0
T1 11 10 0 0
T2 6 5 0 0
T3 1 0 0 0
T4 3 2 0 0
T5 0 9 0 0
T6 0 5 0 0
T7 2 1 0 0
T8 1 0 0 0
T9 1 0 0 0
T15 1 0 0 0
T16 0 3 0 0
T20 0 3 0 0
T27 1 0 0 0
T28 1 0 0 0
T46 0 2 0 0
T48 0 3 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 19230975 19230508 0 0
selKnown1 19230751 19230284 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 19230975 19230508 0 0
T1 20986 20985 0 0
T2 11724 11723 0 0
T3 165 164 0 0
T4 10940 10939 0 0
T7 8729 8728 0 0
T8 1090 1089 0 0
T9 859 858 0 0
T15 16218 16217 0 0
T27 769 768 0 0
T28 160 159 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 19230751 19230284 0 0
T1 20986 20985 0 0
T2 11724 11723 0 0
T3 164 163 0 0
T4 10939 10938 0 0
T7 8729 8728 0 0
T8 1090 1089 0 0
T9 858 857 0 0
T15 16218 16217 0 0
T27 768 767 0 0
T28 159 158 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1813 1346 0 0
selKnown1 1704 1237 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1813 1346 0 0
T1 11 10 0 0
T2 7 6 0 0
T3 1 0 0 0
T4 3 2 0 0
T5 0 17 0 0
T6 0 8 0 0
T7 3 2 0 0
T8 1 0 0 0
T9 1 0 0 0
T15 1 0 0 0
T16 0 3 0 0
T27 1 0 0 0
T28 1 0 0 0
T46 0 2 0 0
T47 0 1 0 0
T48 0 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1704 1237 0 0
T1 11 10 0 0
T2 6 5 0 0
T3 1 0 0 0
T4 3 2 0 0
T5 0 9 0 0
T6 0 5 0 0
T7 2 1 0 0
T8 1 0 0 0
T9 1 0 0 0
T15 1 0 0 0
T16 0 3 0 0
T20 0 3 0 0
T27 1 0 0 0
T28 1 0 0 0
T46 0 2 0 0
T48 0 3 0 0

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