SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
86.94 | 100.00 | 88.89 | 100.00 | 95.83 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1482 | 1482 | 0 | 0 |
OutputsKnown_A | 716319246 | 716039940 | 0 | 0 |
gen_flops.OutputDelay_A | 358159623 | 358013715 | 0 | 2223 |
gen_no_flops.OutputDelay_A | 358159623 | 358019970 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1482 | 1482 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T9 | 6 | 6 | 0 | 0 |
T15 | 6 | 6 | 0 | 0 |
T27 | 6 | 6 | 0 | 0 |
T28 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 716319246 | 716039940 | 0 | 0 |
T1 | 2925192 | 2920434 | 0 | 0 |
T2 | 1016286 | 1014054 | 0 | 0 |
T3 | 33900 | 33318 | 0 | 0 |
T4 | 2932974 | 2931774 | 0 | 0 |
T7 | 2527896 | 2527194 | 0 | 0 |
T8 | 41472 | 41064 | 0 | 0 |
T9 | 118812 | 118482 | 0 | 0 |
T15 | 2458590 | 2458116 | 0 | 0 |
T27 | 134124 | 133668 | 0 | 0 |
T28 | 36618 | 36312 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 358159623 | 358013715 | 0 | 2223 |
T1 | 1462596 | 1460118 | 0 | 9 |
T2 | 508143 | 506973 | 0 | 9 |
T3 | 16950 | 16650 | 0 | 9 |
T4 | 1466487 | 1465860 | 0 | 9 |
T7 | 1263948 | 1263579 | 0 | 9 |
T8 | 20736 | 20523 | 0 | 9 |
T9 | 59406 | 59232 | 0 | 9 |
T15 | 1229295 | 1229049 | 0 | 9 |
T27 | 67062 | 66825 | 0 | 9 |
T28 | 18309 | 18147 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 358159623 | 358019970 | 0 | 0 |
T1 | 1462596 | 1460217 | 0 | 0 |
T2 | 508143 | 507027 | 0 | 0 |
T3 | 16950 | 16659 | 0 | 0 |
T4 | 1466487 | 1465887 | 0 | 0 |
T7 | 1263948 | 1263597 | 0 | 0 |
T8 | 20736 | 20532 | 0 | 0 |
T9 | 59406 | 59241 | 0 | 0 |
T15 | 1229295 | 1229058 | 0 | 0 |
T27 | 67062 | 66834 | 0 | 0 |
T28 | 18309 | 18156 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 119386541 | 119339990 | 0 | 0 |
gen_flops.OutputDelay_A | 119386541 | 119337905 | 0 | 741 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119339990 | 0 | 0 |
T1 | 487532 | 486739 | 0 | 0 |
T2 | 169381 | 169009 | 0 | 0 |
T3 | 5650 | 5553 | 0 | 0 |
T4 | 488829 | 488629 | 0 | 0 |
T7 | 421316 | 421199 | 0 | 0 |
T8 | 6912 | 6844 | 0 | 0 |
T9 | 19802 | 19747 | 0 | 0 |
T15 | 409765 | 409686 | 0 | 0 |
T27 | 22354 | 22278 | 0 | 0 |
T28 | 6103 | 6052 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119337905 | 0 | 741 |
T1 | 487532 | 486706 | 0 | 3 |
T2 | 169381 | 168991 | 0 | 3 |
T3 | 5650 | 5550 | 0 | 3 |
T4 | 488829 | 488620 | 0 | 3 |
T7 | 421316 | 421193 | 0 | 3 |
T8 | 6912 | 6841 | 0 | 3 |
T9 | 19802 | 19744 | 0 | 3 |
T15 | 409765 | 409683 | 0 | 3 |
T27 | 22354 | 22275 | 0 | 3 |
T28 | 6103 | 6049 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 119386541 | 119339990 | 0 | 0 |
gen_flops.OutputDelay_A | 119386541 | 119337905 | 0 | 741 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119339990 | 0 | 0 |
T1 | 487532 | 486739 | 0 | 0 |
T2 | 169381 | 169009 | 0 | 0 |
T3 | 5650 | 5553 | 0 | 0 |
T4 | 488829 | 488629 | 0 | 0 |
T7 | 421316 | 421199 | 0 | 0 |
T8 | 6912 | 6844 | 0 | 0 |
T9 | 19802 | 19747 | 0 | 0 |
T15 | 409765 | 409686 | 0 | 0 |
T27 | 22354 | 22278 | 0 | 0 |
T28 | 6103 | 6052 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119337905 | 0 | 741 |
T1 | 487532 | 486706 | 0 | 3 |
T2 | 169381 | 168991 | 0 | 3 |
T3 | 5650 | 5550 | 0 | 3 |
T4 | 488829 | 488620 | 0 | 3 |
T7 | 421316 | 421193 | 0 | 3 |
T8 | 6912 | 6841 | 0 | 3 |
T9 | 19802 | 19744 | 0 | 3 |
T15 | 409765 | 409683 | 0 | 3 |
T27 | 22354 | 22275 | 0 | 3 |
T28 | 6103 | 6049 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 119386541 | 119339990 | 0 | 0 |
gen_no_flops.OutputDelay_A | 119386541 | 119339990 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119339990 | 0 | 0 |
T1 | 487532 | 486739 | 0 | 0 |
T2 | 169381 | 169009 | 0 | 0 |
T3 | 5650 | 5553 | 0 | 0 |
T4 | 488829 | 488629 | 0 | 0 |
T7 | 421316 | 421199 | 0 | 0 |
T8 | 6912 | 6844 | 0 | 0 |
T9 | 19802 | 19747 | 0 | 0 |
T15 | 409765 | 409686 | 0 | 0 |
T27 | 22354 | 22278 | 0 | 0 |
T28 | 6103 | 6052 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119339990 | 0 | 0 |
T1 | 487532 | 486739 | 0 | 0 |
T2 | 169381 | 169009 | 0 | 0 |
T3 | 5650 | 5553 | 0 | 0 |
T4 | 488829 | 488629 | 0 | 0 |
T7 | 421316 | 421199 | 0 | 0 |
T8 | 6912 | 6844 | 0 | 0 |
T9 | 19802 | 19747 | 0 | 0 |
T15 | 409765 | 409686 | 0 | 0 |
T27 | 22354 | 22278 | 0 | 0 |
T28 | 6103 | 6052 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 119386541 | 119339990 | 0 | 0 |
gen_flops.OutputDelay_A | 119386541 | 119337905 | 0 | 741 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119339990 | 0 | 0 |
T1 | 487532 | 486739 | 0 | 0 |
T2 | 169381 | 169009 | 0 | 0 |
T3 | 5650 | 5553 | 0 | 0 |
T4 | 488829 | 488629 | 0 | 0 |
T7 | 421316 | 421199 | 0 | 0 |
T8 | 6912 | 6844 | 0 | 0 |
T9 | 19802 | 19747 | 0 | 0 |
T15 | 409765 | 409686 | 0 | 0 |
T27 | 22354 | 22278 | 0 | 0 |
T28 | 6103 | 6052 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119337905 | 0 | 741 |
T1 | 487532 | 486706 | 0 | 3 |
T2 | 169381 | 168991 | 0 | 3 |
T3 | 5650 | 5550 | 0 | 3 |
T4 | 488829 | 488620 | 0 | 3 |
T7 | 421316 | 421193 | 0 | 3 |
T8 | 6912 | 6841 | 0 | 3 |
T9 | 19802 | 19744 | 0 | 3 |
T15 | 409765 | 409683 | 0 | 3 |
T27 | 22354 | 22275 | 0 | 3 |
T28 | 6103 | 6049 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 119386541 | 119339990 | 0 | 0 |
gen_no_flops.OutputDelay_A | 119386541 | 119339990 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119339990 | 0 | 0 |
T1 | 487532 | 486739 | 0 | 0 |
T2 | 169381 | 169009 | 0 | 0 |
T3 | 5650 | 5553 | 0 | 0 |
T4 | 488829 | 488629 | 0 | 0 |
T7 | 421316 | 421199 | 0 | 0 |
T8 | 6912 | 6844 | 0 | 0 |
T9 | 19802 | 19747 | 0 | 0 |
T15 | 409765 | 409686 | 0 | 0 |
T27 | 22354 | 22278 | 0 | 0 |
T28 | 6103 | 6052 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119339990 | 0 | 0 |
T1 | 487532 | 486739 | 0 | 0 |
T2 | 169381 | 169009 | 0 | 0 |
T3 | 5650 | 5553 | 0 | 0 |
T4 | 488829 | 488629 | 0 | 0 |
T7 | 421316 | 421199 | 0 | 0 |
T8 | 6912 | 6844 | 0 | 0 |
T9 | 19802 | 19747 | 0 | 0 |
T15 | 409765 | 409686 | 0 | 0 |
T27 | 22354 | 22278 | 0 | 0 |
T28 | 6103 | 6052 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 119386541 | 119339990 | 0 | 0 |
gen_no_flops.OutputDelay_A | 119386541 | 119339990 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119339990 | 0 | 0 |
T1 | 487532 | 486739 | 0 | 0 |
T2 | 169381 | 169009 | 0 | 0 |
T3 | 5650 | 5553 | 0 | 0 |
T4 | 488829 | 488629 | 0 | 0 |
T7 | 421316 | 421199 | 0 | 0 |
T8 | 6912 | 6844 | 0 | 0 |
T9 | 19802 | 19747 | 0 | 0 |
T15 | 409765 | 409686 | 0 | 0 |
T27 | 22354 | 22278 | 0 | 0 |
T28 | 6103 | 6052 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 119386541 | 119339990 | 0 | 0 |
T1 | 487532 | 486739 | 0 | 0 |
T2 | 169381 | 169009 | 0 | 0 |
T3 | 5650 | 5553 | 0 | 0 |
T4 | 488829 | 488629 | 0 | 0 |
T7 | 421316 | 421199 | 0 | 0 |
T8 | 6912 | 6844 | 0 | 0 |
T9 | 19802 | 19747 | 0 | 0 |
T15 | 409765 | 409686 | 0 | 0 |
T27 | 22354 | 22278 | 0 | 0 |
T28 | 6103 | 6052 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |