Line Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 27 | 27 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
ALWAYS | 75 | 10 | 10 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
ALWAYS | 126 | 11 | 11 | 100.00 |
ALWAYS | 169 | 3 | 3 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
90 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
130 |
1 |
1 |
132 |
1 |
1 |
134 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
|
|
|
MISSING_ELSE |
169 |
1 |
1 |
170 |
1 |
1 |
172 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 4 | 66.67 |
Logical | 6 | 4 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 83
EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
-------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
Branch Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
CASE |
79 |
4 |
4 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
CASE |
130 |
5 |
5 |
100.00 |
IF |
169 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 79 case (gen_rz_hs_protocol.src_fsm_q)
-2-: 83 if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-: 93 if (((!src_req_i) || gen_rz_hs_protocol.src_ack))
Branches:
-1- | -2- | -3- | Status | Tests |
LoSt |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
0 |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 130 case (gen_rz_hs_protocol.dst_fsm_q)
-2-: 132 if (gen_rz_hs_protocol.dst_req)
-3-: 137 if (dst_ack_i)
-4-: 145 if ((!gen_rz_hs_protocol.dst_req))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
LoSt |
1 |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
1 |
0 |
- |
Covered |
T1,T2,T3 |
LoSt |
0 |
- |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 169 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231777394 |
111452 |
0 |
0 |
T1 |
508518 |
358 |
0 |
0 |
T2 |
181105 |
158 |
0 |
0 |
T3 |
5814 |
2 |
0 |
0 |
T4 |
499768 |
176 |
0 |
0 |
T7 |
430045 |
140 |
0 |
0 |
T8 |
8002 |
14 |
0 |
0 |
T9 |
20660 |
14 |
0 |
0 |
T15 |
425983 |
280 |
0 |
0 |
T27 |
23122 |
10 |
0 |
0 |
T28 |
6262 |
2 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231777394 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 27 | 27 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
ALWAYS | 75 | 10 | 10 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
ALWAYS | 126 | 11 | 11 | 100.00 |
ALWAYS | 169 | 3 | 3 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
90 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
130 |
1 |
1 |
132 |
1 |
1 |
134 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
|
|
|
MISSING_ELSE |
169 |
1 |
1 |
170 |
1 |
1 |
172 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 4 | 66.67 |
Logical | 6 | 4 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 83
EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
-------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
12 |
92.31 |
CASE |
79 |
4 |
4 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
CASE |
130 |
5 |
4 |
80.00 |
IF |
169 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 79 case (gen_rz_hs_protocol.src_fsm_q)
-2-: 83 if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-: 93 if (((!src_req_i) || gen_rz_hs_protocol.src_ack))
Branches:
-1- | -2- | -3- | Status | Tests |
LoSt |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
0 |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 130 case (gen_rz_hs_protocol.dst_fsm_q)
-2-: 132 if (gen_rz_hs_protocol.dst_req)
-3-: 137 if (dst_ack_i)
-4-: 145 if ((!gen_rz_hs_protocol.dst_req))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
LoSt |
1 |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
1 |
0 |
- |
Not Covered |
|
LoSt |
0 |
- |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 169 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19230751 |
55726 |
0 |
0 |
T1 |
20986 |
179 |
0 |
0 |
T2 |
11724 |
79 |
0 |
0 |
T3 |
164 |
1 |
0 |
0 |
T4 |
10939 |
88 |
0 |
0 |
T7 |
8729 |
70 |
0 |
0 |
T8 |
1090 |
7 |
0 |
0 |
T9 |
858 |
7 |
0 |
0 |
T15 |
16218 |
140 |
0 |
0 |
T27 |
768 |
5 |
0 |
0 |
T28 |
159 |
1 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
212546643 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 27 | 27 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
ALWAYS | 75 | 10 | 10 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
ALWAYS | 126 | 11 | 11 | 100.00 |
ALWAYS | 169 | 3 | 3 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
90 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
130 |
1 |
1 |
132 |
1 |
1 |
134 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
|
|
|
MISSING_ELSE |
169 |
1 |
1 |
170 |
1 |
1 |
172 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 4 | 66.67 |
Logical | 6 | 4 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 83
EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
-------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
CASE |
79 |
4 |
4 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
CASE |
130 |
5 |
5 |
100.00 |
IF |
169 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 79 case (gen_rz_hs_protocol.src_fsm_q)
-2-: 83 if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-: 93 if (((!src_req_i) || gen_rz_hs_protocol.src_ack))
Branches:
-1- | -2- | -3- | Status | Tests |
LoSt |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
0 |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 130 case (gen_rz_hs_protocol.dst_fsm_q)
-2-: 132 if (gen_rz_hs_protocol.dst_req)
-3-: 137 if (dst_ack_i)
-4-: 145 if ((!gen_rz_hs_protocol.dst_req))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
LoSt |
1 |
1 |
- |
Covered |
T1,T2,T3 |
LoSt |
1 |
0 |
- |
Covered |
T1,T2,T3 |
LoSt |
0 |
- |
- |
Covered |
T1,T2,T3 |
HiSt |
- |
- |
1 |
Covered |
T1,T2,T3 |
HiSt |
- |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 169 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
212546643 |
55726 |
0 |
0 |
T1 |
487532 |
179 |
0 |
0 |
T2 |
169381 |
79 |
0 |
0 |
T3 |
5650 |
1 |
0 |
0 |
T4 |
488829 |
88 |
0 |
0 |
T7 |
421316 |
70 |
0 |
0 |
T8 |
6912 |
7 |
0 |
0 |
T9 |
19802 |
7 |
0 |
0 |
T15 |
409765 |
140 |
0 |
0 |
T27 |
22354 |
5 |
0 |
0 |
T28 |
6103 |
1 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19230751 |
0 |
0 |
0 |