Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	952127	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1229412

1

T7

2

T4

4

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	615056	1			T7	3		T4	3		T5	2
values[0x0]	467045	1			T7	2		T4	2		T8	2
values[0x1]	1099438	1			T7	2		T4	2		T5	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	413738	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1767801

1

T7

4

T4

5

T8

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8358	1			T22	217		T10	417		T11	550
valid_sources[0x01]	8494	1			T39	1		T22	253		T10	406
valid_sources[0x02]	8814	1			T22	221		T10	422		T46	1
valid_sources[0x03]	9121	1			T22	268		T10	360		T46	1
valid_sources[0x04]	8732	1			T22	269		T10	387		T19	1
valid_sources[0x05]	8157	1			T22	256		T10	386		T11	596
valid_sources[0x06]	8336	1			T22	245		T10	391		T130	1
valid_sources[0x07]	8781	1			T22	223		T75	2		T10	415
valid_sources[0x08]	8137	1			T22	255		T176	2		T10	436
valid_sources[0x09]	8119	1			T22	271		T10	383		T76	2
valid_sources[0x0a]	8217	1			T22	244		T10	378		T46	2
valid_sources[0x0b]	8545	1			T22	247		T10	432		T11	534
valid_sources[0x0c]	8793	1			T22	230		T10	401		T46	1
valid_sources[0x0d]	9004	1			T22	252		T10	393		T130	2
valid_sources[0x0e]	9123	1			T22	267		T10	427		T11	584
valid_sources[0x0f]	8329	1			T22	251		T10	399		T136	1
valid_sources[0x10]	8156	1			T22	307		T10	404		T46	2
valid_sources[0x11]	9110	1			T22	269		T10	406		T11	574
valid_sources[0x12]	8410	1			T22	225		T10	427		T11	572
valid_sources[0x13]	8274	1			T22	227		T10	397		T141	1
valid_sources[0x14]	8357	1			T22	255		T10	390		T11	582
valid_sources[0x15]	8272	1			T39	1		T22	289		T10	400
valid_sources[0x16]	8923	1			T39	1		T22	240		T10	405
valid_sources[0x17]	9307	1			T22	232		T10	379		T11	629
valid_sources[0x18]	8081	1			T39	2		T22	269		T10	381
valid_sources[0x19]	8219	1			T39	1		T22	251		T10	411
valid_sources[0x1a]	8809	1			T22	257		T176	2		T10	382
valid_sources[0x1b]	8855	1			T39	3		T22	275		T10	402
valid_sources[0x1c]	8564	1			T22	265		T176	1		T10	370
valid_sources[0x1d]	8235	1			T22	253		T10	377		T43	28
valid_sources[0x1e]	8184	1			T22	246		T10	371		T11	597
valid_sources[0x1f]	8652	1			T22	191		T44	2		T10	427
valid_sources[0x20]	7979	1			T39	1		T22	273		T10	391
valid_sources[0x21]	8171	1			T39	1		T22	241		T10	418
valid_sources[0x22]	8584	1			T22	216		T176	1		T10	398
valid_sources[0x23]	8474	1			T39	2		T22	260		T10	414
valid_sources[0x24]	8643	1			T39	1		T22	247		T10	429
valid_sources[0x25]	7966	1			T38	1		T22	253		T10	395
valid_sources[0x26]	9100	1			T22	227		T10	428		T134	4
valid_sources[0x27]	10407	1			T22	222		T10	399		T11	586
valid_sources[0x28]	8353	1			T22	271		T10	408		T11	609
valid_sources[0x29]	8494	1			T22	287		T10	362		T11	602
valid_sources[0x2a]	7976	1			T22	276		T10	404		T130	4
valid_sources[0x2b]	8346	1			T38	5		T22	280		T10	430
valid_sources[0x2c]	8470	1			T22	259		T10	387		T11	570
valid_sources[0x2d]	8594	1			T39	3		T22	252		T10	400
valid_sources[0x2e]	9110	1			T22	252		T10	362		T76	3
valid_sources[0x2f]	8282	1			T6	10		T22	244		T10	398
valid_sources[0x30]	8294	1			T22	256		T10	376		T11	598
valid_sources[0x31]	8235	1			T22	256		T10	405		T134	1
valid_sources[0x32]	8579	1			T22	209		T10	394		T11	586
valid_sources[0x33]	7856	1			T22	215		T10	396		T47	1
valid_sources[0x34]	8146	1			T22	266		T44	3		T10	357
valid_sources[0x35]	8459	1			T22	262		T10	401		T19	1
valid_sources[0x36]	8624	1			T22	275		T10	423		T19	1
valid_sources[0x37]	8363	1			T22	227		T10	366		T11	614
valid_sources[0x38]	9247	1			T22	265		T10	406		T11	621
valid_sources[0x39]	8302	1			T22	263		T10	424		T11	589
valid_sources[0x3a]	10026	1			T22	248		T176	3		T10	403
valid_sources[0x3b]	8060	1			T22	250		T10	378		T11	545
valid_sources[0x3c]	9051	1			T39	1		T22	278		T10	399
valid_sources[0x3d]	8369	1			T22	260		T10	419		T76	1
valid_sources[0x3e]	8457	1			T22	248		T10	407		T130	1
valid_sources[0x3f]	8219	1			T22	277		T10	401		T161	2
valid_sources[0x40]	8548	1			T22	221		T10	393		T134	1
valid_sources[0x41]	8391	1			T4	7		T22	233		T10	373
valid_sources[0x42]	8425	1			T39	1		T22	286		T10	403
valid_sources[0x43]	8943	1			T39	2		T22	280		T10	392
valid_sources[0x44]	8368	1			T39	1		T22	241		T50	1
valid_sources[0x45]	8933	1			T22	270		T10	396		T47	1
valid_sources[0x46]	8146	1			T22	206		T10	406		T11	602
valid_sources[0x47]	8249	1			T39	1		T22	241		T10	398
valid_sources[0x48]	8619	1			T22	234		T10	429		T11	632
valid_sources[0x49]	9413	1			T22	264		T176	1		T10	384
valid_sources[0x4a]	8364	1			T22	248		T10	367		T47	1
valid_sources[0x4b]	8592	1			T39	1		T22	230		T10	407
valid_sources[0x4c]	8404	1			T22	252		T176	1		T10	405
valid_sources[0x4d]	8064	1			T22	250		T176	1		T10	399
valid_sources[0x4e]	8979	1			T5	4		T22	273		T10	395
valid_sources[0x4f]	8229	1			T22	233		T176	1		T10	434
valid_sources[0x50]	8026	1			T39	1		T22	237		T10	376
valid_sources[0x51]	8922	1			T22	240		T10	380		T11	590
valid_sources[0x52]	8324	1			T22	239		T10	399		T19	2
valid_sources[0x53]	8531	1			T38	1		T22	262		T10	394
valid_sources[0x54]	8243	1			T22	213		T10	364		T11	576
valid_sources[0x55]	8554	1			T22	219		T10	367		T11	630
valid_sources[0x56]	8263	1			T22	224		T10	392		T11	601
valid_sources[0x57]	9466	1			T22	232		T10	415		T11	566
valid_sources[0x58]	8450	1			T22	265		T10	419		T11	567
valid_sources[0x59]	8216	1			T22	255		T10	376		T11	646
valid_sources[0x5a]	8484	1			T22	267		T10	389		T11	551
valid_sources[0x5b]	8174	1			T22	226		T10	392		T11	565
valid_sources[0x5c]	8037	1			T22	236		T10	386		T130	1
valid_sources[0x5d]	8821	1			T22	247		T176	1		T10	383
valid_sources[0x5e]	8710	1			T22	243		T10	384		T11	593
valid_sources[0x5f]	8612	1			T22	245		T10	394		T11	561
valid_sources[0x60]	7980	1			T22	226		T10	411		T11	588
valid_sources[0x61]	8563	1			T22	246		T10	431		T19	2
valid_sources[0x62]	8307	1			T22	218		T10	399		T11	637
valid_sources[0x63]	8321	1			T39	3		T22	225		T10	416
valid_sources[0x64]	8102	1			T22	241		T10	417		T11	589
valid_sources[0x65]	8051	1			T22	216		T10	383		T11	591
valid_sources[0x66]	8751	1			T22	265		T10	383		T11	602
valid_sources[0x67]	8283	1			T22	218		T10	413		T11	605
valid_sources[0x68]	8213	1			T22	240		T10	382		T20	1
valid_sources[0x69]	8318	1			T8	1		T22	198		T10	388
valid_sources[0x6a]	8205	1			T22	211		T10	385		T20	2
valid_sources[0x6b]	8088	1			T22	232		T10	386		T131	4
valid_sources[0x6c]	8663	1			T22	273		T10	382		T11	567
valid_sources[0x6d]	8087	1			T22	307		T10	387		T19	1
valid_sources[0x6e]	8443	1			T22	281		T10	387		T11	561
valid_sources[0x6f]	8781	1			T22	247		T10	427		T11	608
valid_sources[0x70]	8251	1			T39	1		T22	258		T10	429
valid_sources[0x71]	8317	1			T22	299		T10	387		T11	554
valid_sources[0x72]	8896	1			T39	1		T22	209		T10	440
valid_sources[0x73]	8240	1			T22	263		T10	376		T11	585
valid_sources[0x74]	8696	1			T22	283		T10	405		T11	613
valid_sources[0x75]	8481	1			T22	258		T10	395		T161	2
valid_sources[0x76]	8592	1			T22	215		T10	417		T11	605
valid_sources[0x77]	8910	1			T39	1		T22	219		T10	393
valid_sources[0x78]	8629	1			T22	213		T10	384		T20	2
valid_sources[0x79]	9095	1			T22	265		T10	400		T46	1
valid_sources[0x7a]	8722	1			T22	254		T10	441		T11	638
valid_sources[0x7b]	8663	1			T22	278		T10	417		T46	1
valid_sources[0x7c]	8286	1			T22	282		T10	372		T47	1
valid_sources[0x7d]	8718	1			T22	256		T10	395		T11	590
valid_sources[0x7e]	9197	1			T22	233		T10	398		T11	558
valid_sources[0x7f]	8906	1			T22	270		T10	431		T19	1
valid_sources[0x80]	8640	1			T22	266		T10	424		T11	572

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

436390

1

T7

2

T4

2

T38

3

values[0x0]

all_enables

biggest_size

396799

1

T4

2

T8

1

T5

3

values[0x1]

all_enables

biggest_size

396223

1

T5

1

T21

1

T22

9851

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46888	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1044093

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	279094	1			T22	10658		T10	18517		T11	27404
values[0x0]	394817	1			T2	1		T3	1		T23	2
values[0x1]	417070	1			T1	1		T27	1		T32	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24518	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1066463

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4474	1			T27	1		T22	145		T10	602
valid_sources[0x01]	3500	1			T6	5		T22	158		T10	118
valid_sources[0x02]	4426	1			T117	1		T22	148		T10	278
valid_sources[0x03]	4181	1			T22	165		T10	963		T146	1
valid_sources[0x04]	4312	1			T22	168		T10	173		T130	2
valid_sources[0x05]	4182	1			T22	184		T10	347		T11	373
valid_sources[0x06]	4190	1			T22	178		T10	462		T177	2
valid_sources[0x07]	3970	1			T22	167		T10	188		T178	5
valid_sources[0x08]	4132	1			T22	175		T10	62		T11	410
valid_sources[0x09]	4374	1			T22	157		T10	431		T11	419
valid_sources[0x0a]	4158	1			T21	9		T22	198		T179	2
valid_sources[0x0b]	4255	1			T38	6		T22	159		T10	727
valid_sources[0x0c]	4777	1			T22	169		T10	35		T11	400
valid_sources[0x0d]	5538	1			T22	180		T10	919		T11	432
valid_sources[0x0e]	5749	1			T22	138		T10	582		T11	501
valid_sources[0x0f]	4875	1			T22	154		T10	303		T11	455
valid_sources[0x10]	5100	1			T22	186		T180	1		T10	717
valid_sources[0x11]	4131	1			T22	175		T10	2		T181	1
valid_sources[0x12]	3859	1			T22	160		T10	161		T11	492
valid_sources[0x13]	4202	1			T22	183		T10	109		T161	1
valid_sources[0x14]	4189	1			T22	176		T10	402		T11	457
valid_sources[0x15]	3918	1			T22	162		T10	192		T11	413
valid_sources[0x16]	4075	1			T22	169		T10	353		T76	1
valid_sources[0x17]	3375	1			T22	151		T10	3		T19	7
valid_sources[0x18]	4902	1			T22	164		T10	302		T130	1
valid_sources[0x19]	4309	1			T22	162		T10	4		T11	410
valid_sources[0x1a]	3289	1			T22	199		T10	223		T178	3
valid_sources[0x1b]	4143	1			T22	170		T10	205		T11	412
valid_sources[0x1c]	4216	1			T22	189		T10	107		T11	453
valid_sources[0x1d]	3927	1			T117	1		T22	177		T10	386
valid_sources[0x1e]	5137	1			T9	1		T22	179		T10	488
valid_sources[0x1f]	4075	1			T22	139		T10	170		T11	428
valid_sources[0x20]	4283	1			T22	162		T10	464		T182	1
valid_sources[0x21]	3262	1			T22	174		T10	4		T11	370
valid_sources[0x22]	4228	1			T22	146		T10	554		T149	1
valid_sources[0x23]	4047	1			T33	1		T22	188		T10	117
valid_sources[0x24]	4409	1			T24	1		T22	186		T10	608
valid_sources[0x25]	3825	1			T22	158		T10	193		T11	433
valid_sources[0x26]	4529	1			T22	180		T10	611		T11	418
valid_sources[0x27]	3412	1			T22	148		T10	8		T11	408
valid_sources[0x28]	4541	1			T22	173		T10	512		T11	467
valid_sources[0x29]	4004	1			T5	1		T22	141		T10	215
valid_sources[0x2a]	4116	1			T22	161		T10	632		T11	339
valid_sources[0x2b]	4527	1			T22	160		T10	131		T11	462
valid_sources[0x2c]	3989	1			T22	150		T10	8		T11	464
valid_sources[0x2d]	4324	1			T22	172		T10	108		T47	3
valid_sources[0x2e]	4419	1			T22	183		T50	1		T10	124
valid_sources[0x2f]	4256	1			T22	159		T10	77		T45	2
valid_sources[0x30]	3990	1			T22	179		T10	76		T11	384
valid_sources[0x31]	3973	1			T22	185		T10	128		T11	418
valid_sources[0x32]	4101	1			T22	163		T10	118		T11	445
valid_sources[0x33]	3461	1			T22	156		T176	5		T20	1
valid_sources[0x34]	4159	1			T22	171		T10	428		T161	1
valid_sources[0x35]	3969	1			T22	179		T10	258		T11	316
valid_sources[0x36]	4552	1			T22	182		T10	454		T183	5
valid_sources[0x37]	4445	1			T22	142		T10	565		T11	467
valid_sources[0x38]	3781	1			T22	160		T10	192		T11	436
valid_sources[0x39]	4504	1			T22	175		T29	8		T10	555
valid_sources[0x3a]	4301	1			T22	185		T10	399		T11	442
valid_sources[0x3b]	4582	1			T22	155		T10	440		T184	1
valid_sources[0x3c]	3925	1			T22	163		T10	226		T11	433
valid_sources[0x3d]	4298	1			T22	148		T10	196		T11	474
valid_sources[0x3e]	4967	1			T22	154		T10	368		T11	467
valid_sources[0x3f]	3970	1			T22	157		T10	3		T11	493
valid_sources[0x40]	4162	1			T22	145		T73	1		T10	105
valid_sources[0x41]	4222	1			T22	132		T10	337		T11	435
valid_sources[0x42]	3876	1			T22	166		T10	447		T11	414
valid_sources[0x43]	3861	1			T23	1		T22	144		T10	280
valid_sources[0x44]	3708	1			T22	151		T10	3		T185	1
valid_sources[0x45]	4720	1			T22	124		T10	643		T186	1
valid_sources[0x46]	4259	1			T22	142		T10	342		T11	437
valid_sources[0x47]	3857	1			T22	152		T46	1		T11	477
valid_sources[0x48]	4268	1			T22	150		T10	344		T11	419
valid_sources[0x49]	4219	1			T22	177		T10	45		T178	2
valid_sources[0x4a]	4224	1			T22	171		T10	1		T11	426
valid_sources[0x4b]	4762	1			T33	1		T22	164		T10	311
valid_sources[0x4c]	4587	1			T22	178		T10	67		T11	444
valid_sources[0x4d]	4021	1			T22	185		T10	8		T47	2
valid_sources[0x4e]	3984	1			T22	172		T10	232		T11	438
valid_sources[0x4f]	4298	1			T22	153		T10	386		T187	1
valid_sources[0x50]	3891	1			T39	1		T22	156		T10	362
valid_sources[0x51]	3765	1			T22	174		T10	439		T11	358
valid_sources[0x52]	4555	1			T22	165		T10	213		T11	408
valid_sources[0x53]	5004	1			T22	153		T10	150		T188	1
valid_sources[0x54]	4885	1			T22	175		T10	190		T11	468
valid_sources[0x55]	4391	1			T22	136		T10	84		T146	1
valid_sources[0x56]	4010	1			T22	149		T10	130		T76	2
valid_sources[0x57]	4024	1			T22	182		T10	127		T11	410
valid_sources[0x58]	4708	1			T22	191		T72	1		T10	406
valid_sources[0x59]	4092	1			T33	1		T22	165		T10	246
valid_sources[0x5a]	3782	1			T22	178		T10	242		T11	461
valid_sources[0x5b]	4150	1			T22	178		T10	355		T11	345
valid_sources[0x5c]	4153	1			T6	2		T22	169		T10	104
valid_sources[0x5d]	3435	1			T22	163		T10	179		T45	1
valid_sources[0x5e]	4711	1			T22	168		T10	423		T146	1
valid_sources[0x5f]	4124	1			T22	159		T10	413		T11	424
valid_sources[0x60]	4466	1			T22	160		T10	163		T11	423
valid_sources[0x61]	4110	1			T22	185		T10	66		T11	443
valid_sources[0x62]	3597	1			T22	146		T10	2		T76	1
valid_sources[0x63]	3906	1			T22	191		T10	218		T11	415
valid_sources[0x64]	4305	1			T22	176		T10	91		T11	403
valid_sources[0x65]	4295	1			T22	180		T10	119		T11	389
valid_sources[0x66]	4779	1			T22	170		T10	1050		T11	438
valid_sources[0x67]	4242	1			T22	141		T10	332		T11	474
valid_sources[0x68]	4070	1			T22	170		T10	76		T11	412
valid_sources[0x69]	3811	1			T67	1		T22	153		T10	1
valid_sources[0x6a]	4741	1			T3	1		T33	1		T22	158
valid_sources[0x6b]	4602	1			T5	1		T22	171		T10	191
valid_sources[0x6c]	3842	1			T4	1		T22	173		T10	268
valid_sources[0x6d]	4222	1			T22	160		T10	673		T161	1
valid_sources[0x6e]	5020	1			T34	1		T22	166		T10	132
valid_sources[0x6f]	4894	1			T65	11		T22	171		T10	182
valid_sources[0x70]	3554	1			T22	201		T10	195		T11	460
valid_sources[0x71]	3835	1			T5	1		T22	177		T10	74
valid_sources[0x72]	4514	1			T22	168		T10	165		T189	1
valid_sources[0x73]	3541	1			T22	150		T10	122		T11	441
valid_sources[0x74]	4295	1			T22	165		T50	2		T143	1
valid_sources[0x75]	3795	1			T22	169		T10	2		T11	434
valid_sources[0x76]	3703	1			T117	1		T22	166		T10	241
valid_sources[0x77]	5405	1			T22	185		T190	2		T10	750
valid_sources[0x78]	4511	1			T22	183		T10	734		T11	404
valid_sources[0x79]	4027	1			T22	143		T10	3		T11	391
valid_sources[0x7a]	4397	1			T22	153		T10	285		T11	420
valid_sources[0x7b]	5395	1			T22	169		T10	1007		T11	381
valid_sources[0x7c]	4893	1			T22	148		T10	101		T11	387
valid_sources[0x7d]	3552	1			T22	132		T50	2		T180	1
valid_sources[0x7e]	4122	1			T22	177		T10	168		T11	429
valid_sources[0x7f]	4228	1			T22	176		T10	193		T11	405
valid_sources[0x80]	3949	1			T8	1		T22	177		T10	203

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

261786

1

T22

10009

T10

17461

T11

25922

values[0x0]

all_enables

biggest_size

390790

1

T2

1

T3

1

T23

2

values[0x1]

all_enables

biggest_size

391517

1

T1

1

T27

1

T32

1