SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5283703 | 1 | T7 | 7 | T4 | 7 | T8 | 2 | ||||
auto[1] | 1965671 | 1 | T39 | 80 | T22 | 83656 | T10 | 129321 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 7249150 | 1 | T7 | 7 | T4 | 7 | T8 | 2 | ||||
values[1] | 16 | 1 | T119 | 1 | T126 | 1 | T162 | 2 | ||||
values[2] | 1 | 1 | T163 | 1 | - | - | - | - | ||||
values[3] | 125 | 1 | T87 | 12 | T119 | 1 | T126 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 7249178 | 1 | T7 | 7 | T4 | 7 | T8 | 2 | ||||
values[1] | 19 | 1 | T120 | 1 | T164 | 4 | T165 | 2 | ||||
values[2] | 7 | 1 | T87 | 1 | T164 | 1 | T165 | 1 | ||||
values[3] | 105 | 1 | T87 | 6 | T119 | 5 | T126 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 7249054 | 1 | T7 | 7 | T4 | 7 | T8 | 2 | ||||
auto[TlIntgErrCmd] | 124 | 1 | T87 | 11 | T119 | 1 | T126 | 6 | ||||
auto[TlIntgErrData] | 96 | 1 | T87 | 4 | T119 | 5 | T126 | 1 | ||||
auto[TlIntgErrBoth] | 100 | 1 | T87 | 5 | T119 | 4 | T126 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 3098485 | 0 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3098282 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
values[1] | 23 | 1 | T87 | 1 | T120 | 1 | T162 | 1 | ||||
values[2] | 4 | 1 | T126 | 1 | T166 | 1 | T167 | 1 | ||||
values[3] | 99 | 1 | T87 | 5 | T119 | 5 | T126 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3098278 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
values[1] | 21 | 1 | T126 | 2 | T120 | 3 | T168 | 1 | ||||
values[2] | 8 | 1 | T164 | 1 | T163 | 1 | T169 | 1 | ||||
values[3] | 92 | 1 | T87 | 5 | T119 | 3 | T126 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3098165 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
auto[TlIntgErrCmd] | 113 | 1 | T87 | 9 | T119 | 7 | T126 | 4 | ||||
auto[TlIntgErrData] | 117 | 1 | T87 | 7 | T119 | 2 | T126 | 2 | ||||
auto[TlIntgErrBoth] | 90 | 1 | T87 | 4 | T119 | 1 | T126 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |