Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
5850657 |
1 |
|
|
T7 |
5 |
|
T4 |
3 |
|
T8 |
1 |
full_word |
1398717 |
1 |
|
|
T7 |
2 |
|
T4 |
4 |
|
T8 |
1 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
7249054 |
1 |
|
|
T7 |
7 |
|
T4 |
7 |
|
T8 |
2 |
auto[TlIntgErrCmd] |
124 |
1 |
|
|
T87 |
11 |
|
T119 |
1 |
|
T126 |
6 |
auto[TlIntgErrData] |
96 |
1 |
|
|
T87 |
4 |
|
T119 |
5 |
|
T126 |
1 |
auto[TlIntgErrBoth] |
100 |
1 |
|
|
T87 |
5 |
|
T119 |
4 |
|
T126 |
3 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
819932 |
1 |
|
|
T7 |
3 |
|
T4 |
3 |
|
T5 |
2 |
auto[1] |
6429442 |
1 |
|
|
T7 |
4 |
|
T4 |
4 |
|
T8 |
2 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
362983 |
1 |
|
|
T7 |
1 |
|
T4 |
1 |
|
T5 |
2 |
auto[TlIntgErrNone] |
partial |
auto[1] |
5487385 |
1 |
|
|
T7 |
4 |
|
T4 |
2 |
|
T8 |
1 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
456825 |
1 |
|
|
T7 |
2 |
|
T4 |
2 |
|
T38 |
3 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
941861 |
1 |
|
|
T4 |
2 |
|
T8 |
1 |
|
T5 |
4 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
49 |
1 |
|
|
T87 |
6 |
|
T119 |
1 |
|
T126 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
67 |
1 |
|
|
T87 |
5 |
|
T126 |
4 |
|
T120 |
5 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
5 |
1 |
|
|
T170 |
1 |
|
T163 |
1 |
|
T169 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
3 |
1 |
|
|
T126 |
1 |
|
T168 |
1 |
|
T171 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
38 |
1 |
|
|
T87 |
2 |
|
T119 |
2 |
|
T120 |
6 |
auto[TlIntgErrData] |
partial |
auto[1] |
47 |
1 |
|
|
T87 |
2 |
|
T119 |
3 |
|
T126 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
3 |
1 |
|
|
T164 |
1 |
|
T172 |
1 |
|
T173 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
8 |
1 |
|
|
T170 |
1 |
|
T168 |
1 |
|
T165 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
26 |
1 |
|
|
T87 |
1 |
|
T126 |
2 |
|
T120 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
62 |
1 |
|
|
T87 |
3 |
|
T119 |
3 |
|
T120 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
3 |
1 |
|
|
T126 |
1 |
|
T163 |
1 |
|
T173 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
9 |
1 |
|
|
T87 |
1 |
|
T119 |
1 |
|
T170 |
1 |