Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	165847077	1476779	0	0
late_debug_enable_rd_A	165847077	24050	0	0
late_debug_enable_regwen_rd_A	165847077	21120	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165847077	1476779	0	0
T10	0	103346	0	0
T11	0	145408	0	0
T12	0	293854	0	0
T13	160911	0	0	0
T14	0	56353	0	0
T17	0	117740	0	0
T18	0	338198	0	0
T22	300083	60938	0	0
T25	257643	0	0	0
T44	10791	0	0	0
T49	0	80897	0	0
T50	507953	0	0	0
T58	0	225218	0	0
T71	2882	0	0	0
T72	219636	0	0	0
T73	131679	0	0	0
T74	169205	0	0	0
T75	21421	0	0	0
T87	0	6	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165847077	24050	0	0
T13	160911	0	0	0
T22	300083	19549	0	0
T25	257643	0	0	0
T44	10791	0	0	0
T50	507953	0	0	0
T60	0	69	0	0
T70	0	104	0	0
T71	2882	0	0	0
T72	219636	0	0	0
T73	131679	0	0	0
T74	169205	0	0	0
T75	21421	0	0	0
T83	0	9	0	0
T92	0	7	0	0
T119	0	32	0	0
T120	0	58	0	0
T121	0	8	0	0
T122	0	37	0	0
T123	0	8	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165847077	21120	0	0
T13	160911	0	0	0
T22	300083	16932	0	0
T25	257643	0	0	0
T44	10791	0	0	0
T50	507953	0	0	0
T60	0	61	0	0
T70	0	78	0	0
T71	2882	0	0	0
T72	219636	0	0	0
T73	131679	0	0	0
T74	169205	0	0	0
T75	21421	0	0	0
T83	0	3	0	0
T92	0	2	0	0
T119	0	44	0	0
T120	0	38	0	0
T122	0	28	0	0
T123	0	8	0	0
T124	0	4	0	0