SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 99927796 | 99869641 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 99927796 | 99867529 | 0 | 741 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99869641 | 0 | 0 |
T1 | 182773 | 182704 | 0 | 0 |
T2 | 631196 | 631130 | 0 | 0 |
T3 | 24664 | 24602 | 0 | 0 |
T7 | 6877 | 6806 | 0 | 0 |
T23 | 303640 | 303447 | 0 | 0 |
T27 | 9805 | 9712 | 0 | 0 |
T32 | 58836 | 58784 | 0 | 0 |
T33 | 4564 | 4509 | 0 | 0 |
T34 | 3339 | 3278 | 0 | 0 |
T35 | 54480 | 53759 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99867529 | 0 | 741 |
T1 | 182773 | 182701 | 0 | 3 |
T2 | 631196 | 631127 | 0 | 3 |
T3 | 24664 | 24599 | 0 | 3 |
T7 | 6877 | 6803 | 0 | 3 |
T23 | 303640 | 303438 | 0 | 3 |
T27 | 9805 | 9709 | 0 | 3 |
T32 | 58836 | 58781 | 0 | 3 |
T33 | 4564 | 4506 | 0 | 3 |
T34 | 3339 | 3275 | 0 | 3 |
T35 | 54480 | 53726 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |