Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
99927796 |
99869641 |
0 |
0 |
T1 |
182773 |
182704 |
0 |
0 |
T2 |
631196 |
631130 |
0 |
0 |
T3 |
24664 |
24602 |
0 |
0 |
T7 |
6877 |
6806 |
0 |
0 |
T23 |
303640 |
303447 |
0 |
0 |
T27 |
9805 |
9712 |
0 |
0 |
T32 |
58836 |
58784 |
0 |
0 |
T33 |
4564 |
4509 |
0 |
0 |
T34 |
3339 |
3278 |
0 |
0 |
T35 |
54480 |
53759 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
99927796 |
99869641 |
0 |
0 |
T1 |
182773 |
182704 |
0 |
0 |
T2 |
631196 |
631130 |
0 |
0 |
T3 |
24664 |
24602 |
0 |
0 |
T7 |
6877 |
6806 |
0 |
0 |
T23 |
303640 |
303447 |
0 |
0 |
T27 |
9805 |
9712 |
0 |
0 |
T32 |
58836 |
58784 |
0 |
0 |
T33 |
4564 |
4509 |
0 |
0 |
T34 |
3339 |
3278 |
0 |
0 |
T35 |
54480 |
53759 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
99927796 |
99869641 |
0 |
0 |
T1 |
182773 |
182704 |
0 |
0 |
T2 |
631196 |
631130 |
0 |
0 |
T3 |
24664 |
24602 |
0 |
0 |
T7 |
6877 |
6806 |
0 |
0 |
T23 |
303640 |
303447 |
0 |
0 |
T27 |
9805 |
9712 |
0 |
0 |
T32 |
58836 |
58784 |
0 |
0 |
T33 |
4564 |
4509 |
0 |
0 |
T34 |
3339 |
3278 |
0 |
0 |
T35 |
54480 |
53759 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
99927796 |
99869641 |
0 |
0 |
T1 |
182773 |
182704 |
0 |
0 |
T2 |
631196 |
631130 |
0 |
0 |
T3 |
24664 |
24602 |
0 |
0 |
T7 |
6877 |
6806 |
0 |
0 |
T23 |
303640 |
303447 |
0 |
0 |
T27 |
9805 |
9712 |
0 |
0 |
T32 |
58836 |
58784 |
0 |
0 |
T33 |
4564 |
4509 |
0 |
0 |
T34 |
3339 |
3278 |
0 |
0 |
T35 |
54480 |
53759 |
0 |
0 |