Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21525232 21523804 0 0
selKnown1 112639849 112638421 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21525232 21523804 0 0
T1 25141 25139 0 0
T2 29345 29343 0 0
T3 13616 13614 0 0
T4 2 0 0 0
T5 0 12 0 0
T6 0 5 0 0
T7 3428 3424 0 0
T9 2 0 0 0
T21 0 14 0 0
T22 0 27 0 0
T23 34462 34458 0 0
T24 6 4 0 0
T27 1121 1117 0 0
T32 35211 35207 0 0
T33 339 335 0 0
T34 384 380 0 0
T35 2882 2878 0 0
T38 0 7 0 0
T54 0 20 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 112639849 112638421 0 0
T1 195343 195341 0 0
T2 645868 645866 0 0
T3 31472 31470 0 0
T4 2 0 0 0
T5 0 10 0 0
T6 0 4 0 0
T7 8590 8588 0 0
T8 2 0 0 0
T9 2 0 0 0
T21 0 14 0 0
T22 0 18 0 0
T23 320874 320870 0 0
T24 6 4 0 0
T27 10363 10361 0 0
T32 76440 76438 0 0
T33 4734 4730 0 0
T34 3532 3528 0 0
T35 55932 55928 0 0
T38 0 6 0 0
T50 0 2 0 0
T53 2 0 0 0
T54 22 20 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8812759 8812512 0 0
selKnown1 99927796 99927549 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8812759 8812512 0 0
T1 12570 12569 0 0
T2 14672 14671 0 0
T3 6808 6807 0 0
T7 1713 1712 0 0
T23 17228 17227 0 0
T27 558 557 0 0
T32 17604 17603 0 0
T33 168 167 0 0
T34 191 190 0 0
T35 1430 1429 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 99927796 99927549 0 0
T1 182773 182772 0 0
T2 631196 631195 0 0
T3 24664 24663 0 0
T7 6877 6876 0 0
T23 303640 303639 0 0
T27 9805 9804 0 0
T32 58836 58835 0 0
T33 4564 4563 0 0
T34 3339 3338 0 0
T35 54480 54479 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 778 531 0 0
selKnown1 704 457 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 778 531 0 0
T4 1 0 0 0
T5 0 5 0 0
T6 0 2 0 0
T7 1 0 0 0
T9 1 0 0 0
T21 0 7 0 0
T22 0 11 0 0
T23 3 2 0 0
T24 3 2 0 0
T27 2 1 0 0
T32 1 0 0 0
T33 1 0 0 0
T34 1 0 0 0
T35 11 10 0 0
T38 0 3 0 0
T54 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 704 457 0 0
T4 1 0 0 0
T5 0 5 0 0
T6 0 2 0 0
T8 1 0 0 0
T9 1 0 0 0
T21 0 7 0 0
T22 0 9 0 0
T23 3 2 0 0
T24 3 2 0 0
T33 1 0 0 0
T34 1 0 0 0
T35 11 10 0 0
T38 0 3 0 0
T50 0 1 0 0
T53 1 0 0 0
T54 11 10 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 12709679 12709212 0 0
selKnown1 12709486 12709019 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 12709679 12709212 0 0
T1 12571 12570 0 0
T2 14673 14672 0 0
T3 6808 6807 0 0
T7 1713 1712 0 0
T23 17228 17227 0 0
T27 559 558 0 0
T32 17605 17604 0 0
T33 169 168 0 0
T34 191 190 0 0
T35 1430 1429 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 12709486 12709019 0 0
T1 12570 12569 0 0
T2 14672 14671 0 0
T3 6808 6807 0 0
T7 1713 1712 0 0
T23 17228 17227 0 0
T27 558 557 0 0
T32 17604 17603 0 0
T33 168 167 0 0
T34 191 190 0 0
T35 1430 1429 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2016 1549 0 0
selKnown1 1863 1396 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2016 1549 0 0
T4 1 0 0 0
T5 0 7 0 0
T6 0 3 0 0
T7 1 0 0 0
T9 1 0 0 0
T21 0 7 0 0
T22 0 16 0 0
T23 3 2 0 0
T24 3 2 0 0
T27 2 1 0 0
T32 1 0 0 0
T33 1 0 0 0
T34 1 0 0 0
T35 11 10 0 0
T38 0 4 0 0
T54 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1863 1396 0 0
T4 1 0 0 0
T5 0 5 0 0
T6 0 2 0 0
T8 1 0 0 0
T9 1 0 0 0
T21 0 7 0 0
T22 0 9 0 0
T23 3 2 0 0
T24 3 2 0 0
T33 1 0 0 0
T34 1 0 0 0
T35 11 10 0 0
T38 0 3 0 0
T50 0 1 0 0
T53 1 0 0 0
T54 11 10 0 0

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