SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.09 | 100.00 | 88.89 | 85.71 | 95.83 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1482 | 1482 | 0 | 0 |
OutputsKnown_A | 599566776 | 599217846 | 0 | 0 |
gen_flops.OutputDelay_A | 299783388 | 299602587 | 0 | 2223 |
gen_no_flops.OutputDelay_A | 299783388 | 299608923 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1482 | 1482 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T23 | 6 | 6 | 0 | 0 |
T27 | 6 | 6 | 0 | 0 |
T32 | 6 | 6 | 0 | 0 |
T33 | 6 | 6 | 0 | 0 |
T34 | 6 | 6 | 0 | 0 |
T35 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 599566776 | 599217846 | 0 | 0 |
T1 | 1096638 | 1096224 | 0 | 0 |
T2 | 3787176 | 3786780 | 0 | 0 |
T3 | 147984 | 147612 | 0 | 0 |
T7 | 41262 | 40836 | 0 | 0 |
T23 | 1821840 | 1820682 | 0 | 0 |
T27 | 58830 | 58272 | 0 | 0 |
T32 | 353016 | 352704 | 0 | 0 |
T33 | 27384 | 27054 | 0 | 0 |
T34 | 20034 | 19668 | 0 | 0 |
T35 | 326880 | 322554 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 299783388 | 299602587 | 0 | 2223 |
T1 | 548319 | 548103 | 0 | 9 |
T2 | 1893588 | 1893381 | 0 | 9 |
T3 | 73992 | 73797 | 0 | 9 |
T7 | 20631 | 20409 | 0 | 9 |
T23 | 910920 | 910314 | 0 | 9 |
T27 | 29415 | 29127 | 0 | 9 |
T32 | 176508 | 176343 | 0 | 9 |
T33 | 13692 | 13518 | 0 | 9 |
T34 | 10017 | 9825 | 0 | 9 |
T35 | 163440 | 161178 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 299783388 | 299608923 | 0 | 0 |
T1 | 548319 | 548112 | 0 | 0 |
T2 | 1893588 | 1893390 | 0 | 0 |
T3 | 73992 | 73806 | 0 | 0 |
T7 | 20631 | 20418 | 0 | 0 |
T23 | 910920 | 910341 | 0 | 0 |
T27 | 29415 | 29136 | 0 | 0 |
T32 | 176508 | 176352 | 0 | 0 |
T33 | 13692 | 13527 | 0 | 0 |
T34 | 10017 | 9834 | 0 | 0 |
T35 | 163440 | 161277 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 99927796 | 99869641 | 0 | 0 |
gen_flops.OutputDelay_A | 99927796 | 99867529 | 0 | 741 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99869641 | 0 | 0 |
T1 | 182773 | 182704 | 0 | 0 |
T2 | 631196 | 631130 | 0 | 0 |
T3 | 24664 | 24602 | 0 | 0 |
T7 | 6877 | 6806 | 0 | 0 |
T23 | 303640 | 303447 | 0 | 0 |
T27 | 9805 | 9712 | 0 | 0 |
T32 | 58836 | 58784 | 0 | 0 |
T33 | 4564 | 4509 | 0 | 0 |
T34 | 3339 | 3278 | 0 | 0 |
T35 | 54480 | 53759 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99867529 | 0 | 741 |
T1 | 182773 | 182701 | 0 | 3 |
T2 | 631196 | 631127 | 0 | 3 |
T3 | 24664 | 24599 | 0 | 3 |
T7 | 6877 | 6803 | 0 | 3 |
T23 | 303640 | 303438 | 0 | 3 |
T27 | 9805 | 9709 | 0 | 3 |
T32 | 58836 | 58781 | 0 | 3 |
T33 | 4564 | 4506 | 0 | 3 |
T34 | 3339 | 3275 | 0 | 3 |
T35 | 54480 | 53726 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 99927796 | 99869641 | 0 | 0 |
gen_flops.OutputDelay_A | 99927796 | 99867529 | 0 | 741 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99869641 | 0 | 0 |
T1 | 182773 | 182704 | 0 | 0 |
T2 | 631196 | 631130 | 0 | 0 |
T3 | 24664 | 24602 | 0 | 0 |
T7 | 6877 | 6806 | 0 | 0 |
T23 | 303640 | 303447 | 0 | 0 |
T27 | 9805 | 9712 | 0 | 0 |
T32 | 58836 | 58784 | 0 | 0 |
T33 | 4564 | 4509 | 0 | 0 |
T34 | 3339 | 3278 | 0 | 0 |
T35 | 54480 | 53759 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99867529 | 0 | 741 |
T1 | 182773 | 182701 | 0 | 3 |
T2 | 631196 | 631127 | 0 | 3 |
T3 | 24664 | 24599 | 0 | 3 |
T7 | 6877 | 6803 | 0 | 3 |
T23 | 303640 | 303438 | 0 | 3 |
T27 | 9805 | 9709 | 0 | 3 |
T32 | 58836 | 58781 | 0 | 3 |
T33 | 4564 | 4506 | 0 | 3 |
T34 | 3339 | 3275 | 0 | 3 |
T35 | 54480 | 53726 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 99927796 | 99869641 | 0 | 0 |
gen_no_flops.OutputDelay_A | 99927796 | 99869641 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99869641 | 0 | 0 |
T1 | 182773 | 182704 | 0 | 0 |
T2 | 631196 | 631130 | 0 | 0 |
T3 | 24664 | 24602 | 0 | 0 |
T7 | 6877 | 6806 | 0 | 0 |
T23 | 303640 | 303447 | 0 | 0 |
T27 | 9805 | 9712 | 0 | 0 |
T32 | 58836 | 58784 | 0 | 0 |
T33 | 4564 | 4509 | 0 | 0 |
T34 | 3339 | 3278 | 0 | 0 |
T35 | 54480 | 53759 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99869641 | 0 | 0 |
T1 | 182773 | 182704 | 0 | 0 |
T2 | 631196 | 631130 | 0 | 0 |
T3 | 24664 | 24602 | 0 | 0 |
T7 | 6877 | 6806 | 0 | 0 |
T23 | 303640 | 303447 | 0 | 0 |
T27 | 9805 | 9712 | 0 | 0 |
T32 | 58836 | 58784 | 0 | 0 |
T33 | 4564 | 4509 | 0 | 0 |
T34 | 3339 | 3278 | 0 | 0 |
T35 | 54480 | 53759 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 99927796 | 99869641 | 0 | 0 |
gen_flops.OutputDelay_A | 99927796 | 99867529 | 0 | 741 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99869641 | 0 | 0 |
T1 | 182773 | 182704 | 0 | 0 |
T2 | 631196 | 631130 | 0 | 0 |
T3 | 24664 | 24602 | 0 | 0 |
T7 | 6877 | 6806 | 0 | 0 |
T23 | 303640 | 303447 | 0 | 0 |
T27 | 9805 | 9712 | 0 | 0 |
T32 | 58836 | 58784 | 0 | 0 |
T33 | 4564 | 4509 | 0 | 0 |
T34 | 3339 | 3278 | 0 | 0 |
T35 | 54480 | 53759 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99867529 | 0 | 741 |
T1 | 182773 | 182701 | 0 | 3 |
T2 | 631196 | 631127 | 0 | 3 |
T3 | 24664 | 24599 | 0 | 3 |
T7 | 6877 | 6803 | 0 | 3 |
T23 | 303640 | 303438 | 0 | 3 |
T27 | 9805 | 9709 | 0 | 3 |
T32 | 58836 | 58781 | 0 | 3 |
T33 | 4564 | 4506 | 0 | 3 |
T34 | 3339 | 3275 | 0 | 3 |
T35 | 54480 | 53726 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 99927796 | 99869641 | 0 | 0 |
gen_no_flops.OutputDelay_A | 99927796 | 99869641 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99869641 | 0 | 0 |
T1 | 182773 | 182704 | 0 | 0 |
T2 | 631196 | 631130 | 0 | 0 |
T3 | 24664 | 24602 | 0 | 0 |
T7 | 6877 | 6806 | 0 | 0 |
T23 | 303640 | 303447 | 0 | 0 |
T27 | 9805 | 9712 | 0 | 0 |
T32 | 58836 | 58784 | 0 | 0 |
T33 | 4564 | 4509 | 0 | 0 |
T34 | 3339 | 3278 | 0 | 0 |
T35 | 54480 | 53759 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99869641 | 0 | 0 |
T1 | 182773 | 182704 | 0 | 0 |
T2 | 631196 | 631130 | 0 | 0 |
T3 | 24664 | 24602 | 0 | 0 |
T7 | 6877 | 6806 | 0 | 0 |
T23 | 303640 | 303447 | 0 | 0 |
T27 | 9805 | 9712 | 0 | 0 |
T32 | 58836 | 58784 | 0 | 0 |
T33 | 4564 | 4509 | 0 | 0 |
T34 | 3339 | 3278 | 0 | 0 |
T35 | 54480 | 53759 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 247 | 247 | 0 | 0 |
OutputsKnown_A | 99927796 | 99869641 | 0 | 0 |
gen_no_flops.OutputDelay_A | 99927796 | 99869641 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 247 | 247 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99869641 | 0 | 0 |
T1 | 182773 | 182704 | 0 | 0 |
T2 | 631196 | 631130 | 0 | 0 |
T3 | 24664 | 24602 | 0 | 0 |
T7 | 6877 | 6806 | 0 | 0 |
T23 | 303640 | 303447 | 0 | 0 |
T27 | 9805 | 9712 | 0 | 0 |
T32 | 58836 | 58784 | 0 | 0 |
T33 | 4564 | 4509 | 0 | 0 |
T34 | 3339 | 3278 | 0 | 0 |
T35 | 54480 | 53759 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99927796 | 99869641 | 0 | 0 |
T1 | 182773 | 182704 | 0 | 0 |
T2 | 631196 | 631130 | 0 | 0 |
T3 | 24664 | 24602 | 0 | 0 |
T7 | 6877 | 6806 | 0 | 0 |
T23 | 303640 | 303447 | 0 | 0 |
T27 | 9805 | 9712 | 0 | 0 |
T32 | 58836 | 58784 | 0 | 0 |
T33 | 4564 | 4509 | 0 | 0 |
T34 | 3339 | 3278 | 0 | 0 |
T35 | 54480 | 53759 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |