Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	553438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

879708

1

T1

53769

T4

2

T6

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	569807	1			T1	16535		T4	1		T6	1
values[0x0]	290030	1			T1	24689		T4	2		T6	3
values[0x1]	573309	1			T1	71091		T6	1		T28	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	283563	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1149583

1

T1

90947

T4

2

T6

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5451	1			T1	416		T8	267		T14	366
valid_sources[0x01]	5251	1			T1	435		T8	259		T14	177
valid_sources[0x02]	5358	1			T1	408		T28	1		T8	297
valid_sources[0x03]	5675	1			T1	447		T8	266		T14	247
valid_sources[0x04]	5817	1			T1	453		T5	1		T8	259
valid_sources[0x05]	4774	1			T1	429		T8	264		T14	203
valid_sources[0x06]	5077	1			T1	472		T5	1		T8	286
valid_sources[0x07]	5972	1			T1	435		T5	1		T8	240
valid_sources[0x08]	5232	1			T1	475		T5	2		T8	250
valid_sources[0x09]	5541	1			T1	467		T8	269		T14	275
valid_sources[0x0a]	5792	1			T1	462		T8	269		T14	270
valid_sources[0x0b]	5312	1			T1	447		T17	1		T8	260
valid_sources[0x0c]	6731	1			T1	461		T8	272		T14	237
valid_sources[0x0d]	5859	1			T1	455		T8	283		T14	255
valid_sources[0x0e]	5834	1			T1	418		T8	249		T14	212
valid_sources[0x0f]	6134	1			T1	385		T5	1		T8	267
valid_sources[0x10]	5447	1			T1	448		T8	296		T14	219
valid_sources[0x11]	5418	1			T1	451		T8	263		T14	289
valid_sources[0x12]	5382	1			T1	483		T8	248		T14	225
valid_sources[0x13]	5481	1			T1	447		T26	35		T8	261
valid_sources[0x14]	5819	1			T1	413		T21	3		T8	258
valid_sources[0x15]	6189	1			T1	422		T8	254		T14	223
valid_sources[0x16]	5250	1			T1	435		T8	218		T14	219
valid_sources[0x17]	5420	1			T1	434		T8	255		T14	245
valid_sources[0x18]	5534	1			T1	466		T8	271		T14	202
valid_sources[0x19]	4983	1			T1	443		T8	267		T11	1
valid_sources[0x1a]	6265	1			T1	439		T5	1		T39	1
valid_sources[0x1b]	5140	1			T1	442		T8	265		T14	193
valid_sources[0x1c]	5422	1			T1	465		T8	286		T11	4
valid_sources[0x1d]	5845	1			T1	457		T5	1		T8	255
valid_sources[0x1e]	5742	1			T1	420		T8	257		T14	342
valid_sources[0x1f]	6049	1			T1	476		T8	264		T169	1
valid_sources[0x20]	5720	1			T1	407		T8	250		T14	253
valid_sources[0x21]	5699	1			T1	411		T8	260		T14	241
valid_sources[0x22]	5287	1			T1	428		T8	264		T75	1
valid_sources[0x23]	5473	1			T1	434		T8	280		T14	212
valid_sources[0x24]	5810	1			T1	434		T40	5		T135	1
valid_sources[0x25]	5456	1			T1	432		T8	271		T15	1
valid_sources[0x26]	5461	1			T1	421		T8	263		T14	292
valid_sources[0x27]	5120	1			T1	428		T8	276		T14	235
valid_sources[0x28]	5382	1			T1	441		T8	270		T14	186
valid_sources[0x29]	5783	1			T1	422		T8	246		T14	206
valid_sources[0x2a]	5978	1			T1	421		T6	1		T8	255
valid_sources[0x2b]	5968	1			T1	423		T8	259		T14	187
valid_sources[0x2c]	5843	1			T1	434		T8	286		T9	1
valid_sources[0x2d]	5601	1			T1	453		T8	256		T9	1
valid_sources[0x2e]	5356	1			T1	475		T8	254		T14	244
valid_sources[0x2f]	5426	1			T1	455		T8	250		T14	182
valid_sources[0x30]	5419	1			T1	407		T8	283		T14	240
valid_sources[0x31]	5900	1			T1	458		T135	2		T8	263
valid_sources[0x32]	5131	1			T1	443		T8	257		T14	145
valid_sources[0x33]	5593	1			T1	432		T41	7		T8	282
valid_sources[0x34]	5304	1			T1	438		T5	1		T8	237
valid_sources[0x35]	5543	1			T1	430		T8	245		T14	261
valid_sources[0x36]	5245	1			T1	464		T28	1		T8	271
valid_sources[0x37]	6022	1			T1	405		T8	275		T169	3
valid_sources[0x38]	5273	1			T1	419		T8	268		T14	201
valid_sources[0x39]	5778	1			T1	443		T8	267		T11	1
valid_sources[0x3a]	5521	1			T1	419		T8	283		T14	104
valid_sources[0x3b]	5546	1			T1	426		T8	255		T9	1
valid_sources[0x3c]	5613	1			T1	462		T39	1		T8	265
valid_sources[0x3d]	5125	1			T1	421		T5	1		T8	272
valid_sources[0x3e]	6776	1			T1	448		T8	281		T13	2
valid_sources[0x3f]	5093	1			T1	475		T8	243		T14	284
valid_sources[0x40]	5622	1			T1	409		T135	1		T8	279
valid_sources[0x41]	5320	1			T1	439		T8	282		T14	308
valid_sources[0x42]	5518	1			T1	443		T5	1		T20	24
valid_sources[0x43]	5827	1			T1	435		T40	3		T8	241
valid_sources[0x44]	5610	1			T1	426		T8	248		T14	223
valid_sources[0x45]	5349	1			T1	413		T8	265		T13	1
valid_sources[0x46]	5232	1			T1	402		T8	245		T9	3
valid_sources[0x47]	5111	1			T1	466		T89	1		T8	267
valid_sources[0x48]	6009	1			T1	464		T10	9		T8	247
valid_sources[0x49]	5321	1			T1	427		T8	282		T14	175
valid_sources[0x4a]	5473	1			T1	411		T8	236		T14	189
valid_sources[0x4b]	5765	1			T1	437		T5	1		T8	264
valid_sources[0x4c]	6011	1			T1	455		T8	260		T14	316
valid_sources[0x4d]	5408	1			T1	412		T5	1		T8	255
valid_sources[0x4e]	5559	1			T1	453		T40	3		T8	269
valid_sources[0x4f]	6021	1			T1	442		T135	1		T8	265
valid_sources[0x50]	5115	1			T1	423		T8	245		T14	238
valid_sources[0x51]	5083	1			T1	445		T8	276		T14	159
valid_sources[0x52]	6009	1			T1	486		T5	1		T8	250
valid_sources[0x53]	6100	1			T1	397		T8	263		T14	395
valid_sources[0x54]	5255	1			T1	458		T8	272		T14	291
valid_sources[0x55]	5822	1			T1	420		T8	262		T14	320
valid_sources[0x56]	5965	1			T1	417		T5	1		T8	269
valid_sources[0x57]	5514	1			T1	465		T8	272		T14	199
valid_sources[0x58]	5653	1			T1	434		T8	259		T14	179
valid_sources[0x59]	5553	1			T1	449		T8	244		T14	265
valid_sources[0x5a]	5966	1			T1	437		T8	235		T9	1
valid_sources[0x5b]	5205	1			T1	418		T8	242		T14	190
valid_sources[0x5c]	5354	1			T1	415		T8	262		T9	1
valid_sources[0x5d]	5456	1			T1	467		T8	247		T14	172
valid_sources[0x5e]	5244	1			T1	444		T8	267		T14	174
valid_sources[0x5f]	5548	1			T1	426		T6	1		T5	1
valid_sources[0x60]	6110	1			T1	432		T8	239		T14	207
valid_sources[0x61]	5601	1			T1	417		T5	1		T8	248
valid_sources[0x62]	5406	1			T1	438		T8	234		T14	187
valid_sources[0x63]	5209	1			T1	371		T5	1		T8	265
valid_sources[0x64]	5655	1			T1	435		T5	1		T8	253
valid_sources[0x65]	5554	1			T1	435		T8	214		T14	154
valid_sources[0x66]	5521	1			T1	443		T8	262		T14	270
valid_sources[0x67]	6079	1			T1	461		T8	255		T14	187
valid_sources[0x68]	5656	1			T1	422		T8	302		T14	208
valid_sources[0x69]	5802	1			T1	454		T8	265		T14	248
valid_sources[0x6a]	5559	1			T1	387		T8	276		T11	2
valid_sources[0x6b]	5411	1			T1	411		T8	271		T14	127
valid_sources[0x6c]	5375	1			T1	410		T8	249		T14	196
valid_sources[0x6d]	5338	1			T1	443		T8	253		T14	276
valid_sources[0x6e]	5826	1			T1	419		T5	1		T8	290
valid_sources[0x6f]	5670	1			T1	423		T8	310		T14	407
valid_sources[0x70]	5343	1			T1	423		T8	253		T150	2
valid_sources[0x71]	5171	1			T1	426		T8	264		T14	189
valid_sources[0x72]	5948	1			T1	466		T6	1		T8	271
valid_sources[0x73]	5481	1			T1	425		T8	254		T14	272
valid_sources[0x74]	5504	1			T1	418		T8	265		T9	1
valid_sources[0x75]	6318	1			T1	452		T8	251		T14	187
valid_sources[0x76]	5738	1			T1	437		T8	257		T22	2
valid_sources[0x77]	5764	1			T1	450		T8	250		T150	1
valid_sources[0x78]	5417	1			T1	447		T8	258		T14	226
valid_sources[0x79]	5641	1			T1	453		T8	248		T14	326
valid_sources[0x7a]	5530	1			T1	417		T5	1		T8	257
valid_sources[0x7b]	5157	1			T1	419		T8	250		T14	151
valid_sources[0x7c]	5388	1			T1	454		T8	251		T11	1
valid_sources[0x7d]	5296	1			T1	411		T8	253		T14	250
valid_sources[0x7e]	5467	1			T1	463		T5	1		T8	276
valid_sources[0x7f]	5607	1			T1	457		T8	284		T14	185
valid_sources[0x80]	4965	1			T1	412		T8	227		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

364977

1

T1

14478

T4

1

T5

2

values[0x0]

all_enables

biggest_size

257657

1

T1

19681

T4

1

T6

3

values[0x1]

all_enables

biggest_size

257074

1

T1

19610

T28

1

T5

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23735	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

470824

1

T1

78204

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	128448	1			T1	20854		T8	12441		T14	10528
values[0x0]	177999	1			T1	29438		T3	1		T33	7
values[0x1]	188112	1			T1	31139		T2	1		T7	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13043	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

481516

1

T1

79825

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1781	1			T1	349		T8	173		T170	3
valid_sources[0x01]	2124	1			T1	330		T6	1		T8	164
valid_sources[0x02]	2029	1			T1	313		T8	176		T14	327
valid_sources[0x03]	2531	1			T1	462		T171	1		T8	173
valid_sources[0x04]	1646	1			T1	296		T8	208		T172	1
valid_sources[0x05]	2319	1			T1	426		T8	175		T173	1
valid_sources[0x06]	2518	1			T1	452		T8	173		T9	1
valid_sources[0x07]	1775	1			T1	311		T5	1		T8	206
valid_sources[0x08]	2045	1			T1	372		T8	202		T14	251
valid_sources[0x09]	1780	1			T1	360		T8	185		T14	7
valid_sources[0x0a]	1971	1			T1	340		T33	1		T8	196
valid_sources[0x0b]	1939	1			T1	323		T8	188		T174	1
valid_sources[0x0c]	1853	1			T1	389		T171	1		T175	1
valid_sources[0x0d]	1804	1			T1	239		T48	1		T65	8
valid_sources[0x0e]	1720	1			T1	312		T8	188		T14	94
valid_sources[0x0f]	1866	1			T1	317		T8	204		T14	251
valid_sources[0x10]	2032	1			T1	356		T83	1		T78	1
valid_sources[0x11]	1519	1			T1	202		T33	1		T24	1
valid_sources[0x12]	1713	1			T1	266		T8	198		T14	7
valid_sources[0x13]	2033	1			T1	314		T8	186		T14	300
valid_sources[0x14]	1980	1			T1	253		T8	207		T9	1
valid_sources[0x15]	2193	1			T1	430		T52	1		T171	1
valid_sources[0x16]	2168	1			T1	432		T8	162		T14	315
valid_sources[0x17]	1491	1			T1	233		T8	217		T14	2
valid_sources[0x18]	1864	1			T1	302		T8	191		T170	1
valid_sources[0x19]	2405	1			T1	370		T18	2		T8	195
valid_sources[0x1a]	1882	1			T1	345		T8	191		T14	225
valid_sources[0x1b]	1978	1			T1	284		T8	197		T176	1
valid_sources[0x1c]	1710	1			T1	203		T33	1		T8	210
valid_sources[0x1d]	2107	1			T1	253		T31	1		T8	163
valid_sources[0x1e]	1808	1			T1	295		T8	175		T9	1
valid_sources[0x1f]	1726	1			T1	377		T8	205		T177	1
valid_sources[0x20]	1769	1			T1	263		T8	197		T14	70
valid_sources[0x21]	1704	1			T1	290		T5	1		T8	190
valid_sources[0x22]	1780	1			T1	296		T8	179		T14	126
valid_sources[0x23]	1693	1			T1	241		T5	1		T48	1
valid_sources[0x24]	1817	1			T1	299		T18	1		T8	216
valid_sources[0x25]	2108	1			T1	363		T8	194		T14	174
valid_sources[0x26]	1810	1			T1	296		T8	192		T11	1
valid_sources[0x27]	1690	1			T1	402		T89	1		T8	175
valid_sources[0x28]	1927	1			T1	378		T52	1		T8	180
valid_sources[0x29]	1868	1			T1	252		T8	192		T9	1
valid_sources[0x2a]	1800	1			T1	286		T67	1		T40	5
valid_sources[0x2b]	1961	1			T1	336		T17	2		T8	203
valid_sources[0x2c]	1618	1			T1	331		T8	203		T14	9
valid_sources[0x2d]	1839	1			T1	311		T33	1		T8	204
valid_sources[0x2e]	1628	1			T1	295		T8	195		T14	68
valid_sources[0x2f]	1774	1			T1	292		T8	219		T14	20
valid_sources[0x30]	1867	1			T1	331		T8	203		T14	234
valid_sources[0x31]	1758	1			T1	270		T8	203		T174	1
valid_sources[0x32]	2079	1			T1	357		T8	183		T132	1
valid_sources[0x33]	1841	1			T1	327		T8	185		T14	124
valid_sources[0x34]	1703	1			T1	339		T8	190		T14	94
valid_sources[0x35]	1970	1			T1	391		T8	182		T133	3
valid_sources[0x36]	1650	1			T1	319		T8	198		T14	57
valid_sources[0x37]	2309	1			T1	388		T171	1		T8	193
valid_sources[0x38]	1898	1			T1	299		T178	4		T8	197
valid_sources[0x39]	2189	1			T1	270		T8	200		T14	141
valid_sources[0x3a]	2269	1			T1	476		T178	2		T8	210
valid_sources[0x3b]	2004	1			T1	359		T8	172		T179	1
valid_sources[0x3c]	1721	1			T1	377		T8	204		T174	1
valid_sources[0x3d]	1874	1			T1	222		T8	187		T14	123
valid_sources[0x3e]	2392	1			T1	309		T33	1		T8	206
valid_sources[0x3f]	2076	1			T1	344		T4	6		T180	1
valid_sources[0x40]	1800	1			T1	301		T18	1		T8	193
valid_sources[0x41]	1997	1			T1	405		T8	203		T70	5
valid_sources[0x42]	1993	1			T1	430		T8	197		T181	1
valid_sources[0x43]	1820	1			T1	252		T171	1		T78	1
valid_sources[0x44]	1694	1			T1	391		T171	1		T8	149
valid_sources[0x45]	1701	1			T1	277		T8	168		T14	200
valid_sources[0x46]	2502	1			T1	390		T140	4		T8	178
valid_sources[0x47]	1815	1			T1	262		T8	161		T14	118
valid_sources[0x48]	2299	1			T1	459		T8	173		T70	2
valid_sources[0x49]	1713	1			T1	236		T48	2		T78	2
valid_sources[0x4a]	1855	1			T1	355		T8	176		T11	1
valid_sources[0x4b]	2596	1			T1	461		T8	210		T14	270
valid_sources[0x4c]	1878	1			T1	408		T48	1		T8	173
valid_sources[0x4d]	1586	1			T1	218		T171	1		T8	205
valid_sources[0x4e]	1855	1			T1	281		T101	1		T8	175
valid_sources[0x4f]	1720	1			T1	284		T8	199		T72	1
valid_sources[0x50]	2404	1			T1	427		T8	208		T182	14
valid_sources[0x51]	2130	1			T1	335		T8	191		T14	54
valid_sources[0x52]	2143	1			T1	363		T8	168		T14	523
valid_sources[0x53]	1879	1			T1	391		T8	207		T14	229
valid_sources[0x54]	1941	1			T1	421		T180	1		T8	206
valid_sources[0x55]	1770	1			T1	286		T8	190		T11	1
valid_sources[0x56]	2033	1			T1	270		T2	1		T8	192
valid_sources[0x57]	1701	1			T1	217		T8	191		T14	116
valid_sources[0x58]	2052	1			T1	220		T78	3		T8	201
valid_sources[0x59]	2189	1			T1	341		T8	178		T173	1
valid_sources[0x5a]	1721	1			T1	312		T183	1		T20	1
valid_sources[0x5b]	1614	1			T1	229		T8	173		T14	19
valid_sources[0x5c]	1865	1			T1	447		T180	2		T8	186
valid_sources[0x5d]	1986	1			T1	375		T8	184		T14	224
valid_sources[0x5e]	2084	1			T1	451		T33	2		T8	190
valid_sources[0x5f]	2267	1			T1	434		T8	172		T14	216
valid_sources[0x60]	1636	1			T1	327		T8	219		T14	6
valid_sources[0x61]	1695	1			T1	335		T48	1		T171	1
valid_sources[0x62]	1946	1			T1	263		T171	1		T184	2
valid_sources[0x63]	1902	1			T1	341		T8	203		T150	1
valid_sources[0x64]	1891	1			T1	343		T8	173		T14	186
valid_sources[0x65]	1704	1			T1	277		T8	164		T173	2
valid_sources[0x66]	2057	1			T1	336		T20	1		T8	189
valid_sources[0x67]	2192	1			T1	275		T8	173		T14	379
valid_sources[0x68]	2075	1			T1	442		T41	1		T8	217
valid_sources[0x69]	1949	1			T1	340		T171	1		T8	187
valid_sources[0x6a]	1673	1			T1	272		T47	1		T28	1
valid_sources[0x6b]	1875	1			T1	256		T8	205		T14	329
valid_sources[0x6c]	2038	1			T1	234		T33	1		T10	4
valid_sources[0x6d]	1787	1			T1	296		T8	158		T14	228
valid_sources[0x6e]	1841	1			T1	331		T40	2		T8	200
valid_sources[0x6f]	1796	1			T1	385		T8	189		T14	40
valid_sources[0x70]	1941	1			T1	297		T48	1		T8	205
valid_sources[0x71]	2465	1			T1	280		T52	1		T171	1
valid_sources[0x72]	1877	1			T1	435		T136	1		T8	186
valid_sources[0x73]	1910	1			T1	359		T8	199		T14	159
valid_sources[0x74]	1664	1			T1	336		T8	177		T14	31
valid_sources[0x75]	2270	1			T1	319		T5	1		T8	226
valid_sources[0x76]	2119	1			T1	344		T8	211		T13	1
valid_sources[0x77]	1815	1			T1	338		T8	189		T14	161
valid_sources[0x78]	2174	1			T1	382		T8	198		T14	350
valid_sources[0x79]	2073	1			T1	249		T8	184		T14	302
valid_sources[0x7a]	1532	1			T1	228		T23	2		T31	2
valid_sources[0x7b]	1894	1			T1	265		T185	1		T8	220
valid_sources[0x7c]	1798	1			T1	285		T8	145		T14	4
valid_sources[0x7d]	2082	1			T1	408		T33	1		T8	178
valid_sources[0x7e]	2005	1			T1	270		T8	198		T14	191
valid_sources[0x7f]	2038	1			T1	257		T8	194		T170	1
valid_sources[0x80]	2438	1			T1	346		T8	172		T14	263

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

119125

1

T1

19754

T8

11665

T14

9950

values[0x0]

all_enables

biggest_size

175825

1

T1

29207

T3

1

T33

3

values[0x1]

all_enables

biggest_size

175874

1

T1

29243

T2

1

T7

1