SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2834414 | 1 | T1 | 340772 | T4 | 3 | T6 | 5 | ||||
auto[1] | 898447 | 1 | T1 | 147878 | T8 | 93031 | T14 | 82330 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3732638 | 1 | T1 | 488650 | T4 | 3 | T6 | 5 | ||||
values[1] | 22 | 1 | T85 | 2 | T88 | 1 | T154 | 1 | ||||
values[2] | 3 | 1 | T155 | 1 | T156 | 1 | T157 | 1 | ||||
values[3] | 123 | 1 | T85 | 9 | T87 | 6 | T88 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3732634 | 1 | T1 | 488650 | T4 | 3 | T6 | 5 | ||||
values[1] | 23 | 1 | T85 | 1 | T87 | 1 | T154 | 1 | ||||
values[2] | 4 | 1 | T87 | 1 | T155 | 2 | T158 | 1 | ||||
values[3] | 112 | 1 | T85 | 10 | T87 | 6 | T88 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3732531 | 1 | T1 | 488650 | T4 | 3 | T6 | 5 | ||||
auto[TlIntgErrCmd] | 103 | 1 | T85 | 2 | T87 | 5 | T88 | 6 | ||||
auto[TlIntgErrData] | 107 | 1 | T85 | 9 | T87 | 8 | T88 | 5 | ||||
auto[TlIntgErrBoth] | 120 | 1 | T85 | 9 | T87 | 7 | T88 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 1395437 | 0 | T1 | 229319 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1395214 | 1 | T1 | 229319 | T2 | 1 | T3 | 1 | ||||
values[1] | 22 | 1 | T85 | 3 | T87 | 1 | T88 | 1 | ||||
values[2] | 3 | 1 | T87 | 1 | T157 | 1 | T158 | 1 | ||||
values[3] | 116 | 1 | T85 | 7 | T87 | 8 | T88 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1395214 | 1 | T1 | 229319 | T2 | 1 | T3 | 1 | ||||
values[1] | 23 | 1 | T85 | 1 | T87 | 1 | T88 | 5 | ||||
values[2] | 6 | 1 | T85 | 1 | T159 | 2 | T160 | 1 | ||||
values[3] | 115 | 1 | T85 | 7 | T87 | 10 | T88 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1395107 | 1 | T1 | 229319 | T2 | 1 | T3 | 1 | ||||
auto[TlIntgErrCmd] | 107 | 1 | T85 | 5 | T87 | 4 | T88 | 6 | ||||
auto[TlIntgErrData] | 107 | 1 | T85 | 6 | T87 | 6 | T88 | 3 | ||||
auto[TlIntgErrBoth] | 116 | 1 | T85 | 9 | T87 | 10 | T88 | 11 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |