Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2774548

1

T1

422044

T4

1

T6

2

full_word

958313

1

T1

66606

T4

2

T6

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3732531	1			T1	488650		T4	3		T6	5
auto[TlIntgErrCmd]	103	1			T85	2		T87	5		T88	6
auto[TlIntgErrData]	107	1			T85	9		T87	8		T88	5
auto[TlIntgErrBoth]	120	1			T85	9		T87	7		T88	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

664727

1

T1

31850

T4

1

T6

1

auto[1]

3068134

1

T1

456800

T4

2

T6

4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	290178	1			T1	15845		T6	1		T28	2
auto[TlIntgErrNone]	partial	auto[1]	2484062	1			T1	406199		T4	1		T6	1
auto[TlIntgErrNone]	full_word	auto[0]	374402	1			T1	16005		T4	1		T5	2
auto[TlIntgErrNone]	full_word	auto[1]	583889	1			T1	50601		T4	1		T6	3
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T85	1		T87	1		T88	4
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T87	4		T88	2		T154	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T85	1		T157	1		T158	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T161	1		T162	1		T158	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T85	6		T87	3		T88	4
auto[TlIntgErrData]	partial	auto[1]	51	1			T85	3		T87	5		T88	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T163	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T154	2		T161	2		T164	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T85	4		T87	4		T88	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T85	4		T87	2		T88	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T85	1		T165	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T87	1		T88	1		T155	1