Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 150561781 662277 0 0
late_debug_enable_rd_A 150561781 2772 0 0
late_debug_enable_regwen_rd_A 150561781 3681 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 150561781 662277 0 0
T1 334305 109790 0 0
T2 345160 0 0 0
T3 82115 0 0 0
T4 181049 0 0 0
T6 101648 0 0 0
T7 6615 0 0 0
T8 0 68983 0 0
T12 50299 0 0 0
T14 0 54781 0 0
T19 0 259119 0 0
T23 191867 0 0 0
T33 1481 0 0 0
T34 47001 0 0 0
T55 0 30975 0 0
T56 0 107025 0 0
T60 0 214 0 0
T85 0 4 0 0
T86 0 453 0 0
T87 0 3 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 150561781 2772 0 0
T60 849228 182 0 0
T85 213779 76 0 0
T91 12657 9 0 0
T92 57442 18 0 0
T100 23683 41 0 0
T106 49462 16 0 0
T128 18306 35 0 0
T129 23271 204 0 0
T130 28778 271 0 0
T131 26091 217 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 150561781 3681 0 0
T60 849228 188 0 0
T85 213779 104 0 0
T91 12657 11 0 0
T92 57442 43 0 0
T100 23683 38 0 0
T106 49462 12 0 0
T128 18306 36 0 0
T129 23271 258 0 0
T130 28778 211 0 0
T131 26091 144 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%