Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
17750901 |
17749487 |
0 |
0 |
selKnown1 |
88795805 |
88794391 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17750901 |
17749487 |
0 |
0 |
T1 |
754681 |
754677 |
0 |
0 |
T2 |
24351 |
24347 |
0 |
0 |
T3 |
36372 |
36368 |
0 |
0 |
T4 |
21941 |
21937 |
0 |
0 |
T5 |
0 |
12 |
0 |
0 |
T6 |
23995 |
23991 |
0 |
0 |
T7 |
2924 |
2920 |
0 |
0 |
T12 |
20692 |
20688 |
0 |
0 |
T17 |
0 |
6 |
0 |
0 |
T18 |
0 |
9 |
0 |
0 |
T23 |
14595 |
14591 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T33 |
1077 |
1073 |
0 |
0 |
T34 |
16557 |
16553 |
0 |
0 |
T52 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
88795805 |
88794391 |
0 |
0 |
T1 |
711652 |
711649 |
0 |
0 |
T2 |
357336 |
357332 |
0 |
0 |
T3 |
100302 |
100298 |
0 |
0 |
T4 |
192022 |
192018 |
0 |
0 |
T5 |
0 |
10 |
0 |
0 |
T6 |
113649 |
113645 |
0 |
0 |
T7 |
8078 |
8074 |
0 |
0 |
T12 |
60646 |
60642 |
0 |
0 |
T17 |
0 |
6 |
0 |
0 |
T18 |
0 |
8 |
0 |
0 |
T23 |
199167 |
199163 |
0 |
0 |
T26 |
0 |
6 |
0 |
0 |
T28 |
0 |
4 |
0 |
0 |
T33 |
2020 |
2016 |
0 |
0 |
T34 |
55280 |
55276 |
0 |
0 |
T52 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6788475 |
6788231 |
0 |
0 |
selKnown1 |
77833775 |
77833531 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6788475 |
6788231 |
0 |
0 |
T1 |
377325 |
377324 |
0 |
0 |
T2 |
12174 |
12173 |
0 |
0 |
T3 |
18185 |
18184 |
0 |
0 |
T4 |
10965 |
10964 |
0 |
0 |
T6 |
11985 |
11984 |
0 |
0 |
T7 |
1461 |
1460 |
0 |
0 |
T12 |
10345 |
10344 |
0 |
0 |
T23 |
7294 |
7293 |
0 |
0 |
T33 |
537 |
536 |
0 |
0 |
T34 |
8277 |
8276 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77833775 |
77833531 |
0 |
0 |
T1 |
334305 |
334305 |
0 |
0 |
T2 |
345160 |
345159 |
0 |
0 |
T3 |
82115 |
82114 |
0 |
0 |
T4 |
181049 |
181048 |
0 |
0 |
T6 |
101648 |
101647 |
0 |
0 |
T7 |
6615 |
6614 |
0 |
0 |
T12 |
50299 |
50298 |
0 |
0 |
T23 |
191867 |
191866 |
0 |
0 |
T33 |
1481 |
1480 |
0 |
0 |
T34 |
47001 |
47000 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
755 |
511 |
0 |
0 |
T1 |
14 |
13 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
0 |
6 |
0 |
0 |
T6 |
11 |
10 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T17 |
0 |
3 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
3 |
2 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
0 |
4 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T52 |
0 |
3 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
694 |
450 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
0 |
5 |
0 |
0 |
T6 |
8 |
7 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T17 |
0 |
3 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
3 |
2 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T52 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10959704 |
10959241 |
0 |
0 |
selKnown1 |
10959489 |
10959026 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10959704 |
10959241 |
0 |
0 |
T1 |
377325 |
377324 |
0 |
0 |
T2 |
12175 |
12174 |
0 |
0 |
T3 |
18185 |
18184 |
0 |
0 |
T4 |
10966 |
10965 |
0 |
0 |
T6 |
11986 |
11985 |
0 |
0 |
T7 |
1461 |
1460 |
0 |
0 |
T12 |
10345 |
10344 |
0 |
0 |
T23 |
7295 |
7294 |
0 |
0 |
T33 |
538 |
537 |
0 |
0 |
T34 |
8278 |
8277 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10959489 |
10959026 |
0 |
0 |
T1 |
377325 |
377324 |
0 |
0 |
T2 |
12174 |
12173 |
0 |
0 |
T3 |
18185 |
18184 |
0 |
0 |
T4 |
10965 |
10964 |
0 |
0 |
T6 |
11985 |
11984 |
0 |
0 |
T7 |
1461 |
1460 |
0 |
0 |
T12 |
10345 |
10344 |
0 |
0 |
T23 |
7294 |
7293 |
0 |
0 |
T33 |
537 |
536 |
0 |
0 |
T34 |
8277 |
8276 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1967 |
1504 |
0 |
0 |
selKnown1 |
1847 |
1384 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1967 |
1504 |
0 |
0 |
T1 |
17 |
16 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
0 |
6 |
0 |
0 |
T6 |
13 |
12 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T17 |
0 |
3 |
0 |
0 |
T18 |
0 |
5 |
0 |
0 |
T23 |
3 |
2 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T52 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1847 |
1384 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
0 |
5 |
0 |
0 |
T6 |
8 |
7 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T17 |
0 |
3 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
3 |
2 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T52 |
0 |
3 |
0 |
0 |