SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
86.94 | 100.00 | 88.89 | 100.00 | 95.83 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1464 | 1464 | 0 | 0 |
OutputsKnown_A | 467002650 | 466713330 | 0 | 0 |
gen_flops.OutputDelay_A | 233501325 | 233350419 | 0 | 2196 |
gen_no_flops.OutputDelay_A | 233501325 | 233356665 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1464 | 1464 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
T23 | 6 | 6 | 0 | 0 |
T33 | 6 | 6 | 0 | 0 |
T34 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 467002650 | 466713330 | 0 | 0 |
T1 | 2005830 | 2005200 | 0 | 0 |
T2 | 2070960 | 2070660 | 0 | 0 |
T3 | 492690 | 492384 | 0 | 0 |
T4 | 1086294 | 1084626 | 0 | 0 |
T6 | 609888 | 606750 | 0 | 0 |
T7 | 39690 | 39348 | 0 | 0 |
T12 | 301794 | 301248 | 0 | 0 |
T23 | 1151202 | 1150176 | 0 | 0 |
T33 | 8886 | 8394 | 0 | 0 |
T34 | 282006 | 281646 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 233501325 | 233350419 | 0 | 2196 |
T1 | 1002915 | 1002588 | 0 | 9 |
T2 | 1035480 | 1035321 | 0 | 9 |
T3 | 246345 | 246183 | 0 | 9 |
T4 | 543147 | 542277 | 0 | 9 |
T6 | 304944 | 303303 | 0 | 9 |
T7 | 19845 | 19665 | 0 | 9 |
T12 | 150897 | 150615 | 0 | 9 |
T23 | 575601 | 575061 | 0 | 9 |
T33 | 4443 | 4188 | 0 | 9 |
T34 | 141003 | 140814 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 233501325 | 233356665 | 0 | 0 |
T1 | 1002915 | 1002600 | 0 | 0 |
T2 | 1035480 | 1035330 | 0 | 0 |
T3 | 246345 | 246192 | 0 | 0 |
T4 | 543147 | 542313 | 0 | 0 |
T6 | 304944 | 303375 | 0 | 0 |
T7 | 19845 | 19674 | 0 | 0 |
T12 | 150897 | 150624 | 0 | 0 |
T23 | 575601 | 575088 | 0 | 0 |
T33 | 4443 | 4197 | 0 | 0 |
T34 | 141003 | 140823 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 244 | 244 | 0 | 0 |
OutputsKnown_A | 77833775 | 77785555 | 0 | 0 |
gen_flops.OutputDelay_A | 77833775 | 77783473 | 0 | 732 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 244 | 244 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77785555 | 0 | 0 |
T1 | 334305 | 334200 | 0 | 0 |
T2 | 345160 | 345110 | 0 | 0 |
T3 | 82115 | 82064 | 0 | 0 |
T4 | 181049 | 180771 | 0 | 0 |
T6 | 101648 | 101125 | 0 | 0 |
T7 | 6615 | 6558 | 0 | 0 |
T12 | 50299 | 50208 | 0 | 0 |
T23 | 191867 | 191696 | 0 | 0 |
T33 | 1481 | 1399 | 0 | 0 |
T34 | 47001 | 46941 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77783473 | 0 | 732 |
T1 | 334305 | 334196 | 0 | 3 |
T2 | 345160 | 345107 | 0 | 3 |
T3 | 82115 | 82061 | 0 | 3 |
T4 | 181049 | 180759 | 0 | 3 |
T6 | 101648 | 101101 | 0 | 3 |
T7 | 6615 | 6555 | 0 | 3 |
T12 | 50299 | 50205 | 0 | 3 |
T23 | 191867 | 191687 | 0 | 3 |
T33 | 1481 | 1396 | 0 | 3 |
T34 | 47001 | 46938 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 244 | 244 | 0 | 0 |
OutputsKnown_A | 77833775 | 77785555 | 0 | 0 |
gen_flops.OutputDelay_A | 77833775 | 77783473 | 0 | 732 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 244 | 244 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77785555 | 0 | 0 |
T1 | 334305 | 334200 | 0 | 0 |
T2 | 345160 | 345110 | 0 | 0 |
T3 | 82115 | 82064 | 0 | 0 |
T4 | 181049 | 180771 | 0 | 0 |
T6 | 101648 | 101125 | 0 | 0 |
T7 | 6615 | 6558 | 0 | 0 |
T12 | 50299 | 50208 | 0 | 0 |
T23 | 191867 | 191696 | 0 | 0 |
T33 | 1481 | 1399 | 0 | 0 |
T34 | 47001 | 46941 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77783473 | 0 | 732 |
T1 | 334305 | 334196 | 0 | 3 |
T2 | 345160 | 345107 | 0 | 3 |
T3 | 82115 | 82061 | 0 | 3 |
T4 | 181049 | 180759 | 0 | 3 |
T6 | 101648 | 101101 | 0 | 3 |
T7 | 6615 | 6555 | 0 | 3 |
T12 | 50299 | 50205 | 0 | 3 |
T23 | 191867 | 191687 | 0 | 3 |
T33 | 1481 | 1396 | 0 | 3 |
T34 | 47001 | 46938 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 244 | 244 | 0 | 0 |
OutputsKnown_A | 77833775 | 77785555 | 0 | 0 |
gen_no_flops.OutputDelay_A | 77833775 | 77785555 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 244 | 244 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77785555 | 0 | 0 |
T1 | 334305 | 334200 | 0 | 0 |
T2 | 345160 | 345110 | 0 | 0 |
T3 | 82115 | 82064 | 0 | 0 |
T4 | 181049 | 180771 | 0 | 0 |
T6 | 101648 | 101125 | 0 | 0 |
T7 | 6615 | 6558 | 0 | 0 |
T12 | 50299 | 50208 | 0 | 0 |
T23 | 191867 | 191696 | 0 | 0 |
T33 | 1481 | 1399 | 0 | 0 |
T34 | 47001 | 46941 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77785555 | 0 | 0 |
T1 | 334305 | 334200 | 0 | 0 |
T2 | 345160 | 345110 | 0 | 0 |
T3 | 82115 | 82064 | 0 | 0 |
T4 | 181049 | 180771 | 0 | 0 |
T6 | 101648 | 101125 | 0 | 0 |
T7 | 6615 | 6558 | 0 | 0 |
T12 | 50299 | 50208 | 0 | 0 |
T23 | 191867 | 191696 | 0 | 0 |
T33 | 1481 | 1399 | 0 | 0 |
T34 | 47001 | 46941 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 244 | 244 | 0 | 0 |
OutputsKnown_A | 77833775 | 77785555 | 0 | 0 |
gen_flops.OutputDelay_A | 77833775 | 77783473 | 0 | 732 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 244 | 244 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77785555 | 0 | 0 |
T1 | 334305 | 334200 | 0 | 0 |
T2 | 345160 | 345110 | 0 | 0 |
T3 | 82115 | 82064 | 0 | 0 |
T4 | 181049 | 180771 | 0 | 0 |
T6 | 101648 | 101125 | 0 | 0 |
T7 | 6615 | 6558 | 0 | 0 |
T12 | 50299 | 50208 | 0 | 0 |
T23 | 191867 | 191696 | 0 | 0 |
T33 | 1481 | 1399 | 0 | 0 |
T34 | 47001 | 46941 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77783473 | 0 | 732 |
T1 | 334305 | 334196 | 0 | 3 |
T2 | 345160 | 345107 | 0 | 3 |
T3 | 82115 | 82061 | 0 | 3 |
T4 | 181049 | 180759 | 0 | 3 |
T6 | 101648 | 101101 | 0 | 3 |
T7 | 6615 | 6555 | 0 | 3 |
T12 | 50299 | 50205 | 0 | 3 |
T23 | 191867 | 191687 | 0 | 3 |
T33 | 1481 | 1396 | 0 | 3 |
T34 | 47001 | 46938 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 244 | 244 | 0 | 0 |
OutputsKnown_A | 77833775 | 77785555 | 0 | 0 |
gen_no_flops.OutputDelay_A | 77833775 | 77785555 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 244 | 244 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77785555 | 0 | 0 |
T1 | 334305 | 334200 | 0 | 0 |
T2 | 345160 | 345110 | 0 | 0 |
T3 | 82115 | 82064 | 0 | 0 |
T4 | 181049 | 180771 | 0 | 0 |
T6 | 101648 | 101125 | 0 | 0 |
T7 | 6615 | 6558 | 0 | 0 |
T12 | 50299 | 50208 | 0 | 0 |
T23 | 191867 | 191696 | 0 | 0 |
T33 | 1481 | 1399 | 0 | 0 |
T34 | 47001 | 46941 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77785555 | 0 | 0 |
T1 | 334305 | 334200 | 0 | 0 |
T2 | 345160 | 345110 | 0 | 0 |
T3 | 82115 | 82064 | 0 | 0 |
T4 | 181049 | 180771 | 0 | 0 |
T6 | 101648 | 101125 | 0 | 0 |
T7 | 6615 | 6558 | 0 | 0 |
T12 | 50299 | 50208 | 0 | 0 |
T23 | 191867 | 191696 | 0 | 0 |
T33 | 1481 | 1399 | 0 | 0 |
T34 | 47001 | 46941 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 244 | 244 | 0 | 0 |
OutputsKnown_A | 77833775 | 77785555 | 0 | 0 |
gen_no_flops.OutputDelay_A | 77833775 | 77785555 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 244 | 244 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77785555 | 0 | 0 |
T1 | 334305 | 334200 | 0 | 0 |
T2 | 345160 | 345110 | 0 | 0 |
T3 | 82115 | 82064 | 0 | 0 |
T4 | 181049 | 180771 | 0 | 0 |
T6 | 101648 | 101125 | 0 | 0 |
T7 | 6615 | 6558 | 0 | 0 |
T12 | 50299 | 50208 | 0 | 0 |
T23 | 191867 | 191696 | 0 | 0 |
T33 | 1481 | 1399 | 0 | 0 |
T34 | 47001 | 46941 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 77833775 | 77785555 | 0 | 0 |
T1 | 334305 | 334200 | 0 | 0 |
T2 | 345160 | 345110 | 0 | 0 |
T3 | 82115 | 82064 | 0 | 0 |
T4 | 181049 | 180771 | 0 | 0 |
T6 | 101648 | 101125 | 0 | 0 |
T7 | 6615 | 6558 | 0 | 0 |
T12 | 50299 | 50208 | 0 | 0 |
T23 | 191867 | 191696 | 0 | 0 |
T33 | 1481 | 1399 | 0 | 0 |
T34 | 47001 | 46941 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |