Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	664125	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

978232

1

T1

3

T2

5

T24

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	601463	1			T1	3		T2	6		T24	1
values[0x0]	335763	1			T1	3		T2	7		T3	1
values[0x1]	705131	1			T1	2		T2	6		T24	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	324570	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1317787

1

T1

3

T2

8

T24

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5849	1			T38	1		T17	612		T6	729
valid_sources[0x01]	6585	1			T17	598		T6	794		T9	311
valid_sources[0x02]	6165	1			T17	542		T6	723		T9	367
valid_sources[0x03]	6348	1			T17	619		T6	749		T9	296
valid_sources[0x04]	6322	1			T17	617		T58	1		T6	822
valid_sources[0x05]	7132	1			T17	607		T6	755		T9	308
valid_sources[0x06]	6644	1			T16	1		T17	554		T6	775
valid_sources[0x07]	6996	1			T17	635		T58	1		T6	756
valid_sources[0x08]	6371	1			T17	614		T6	790		T9	433
valid_sources[0x09]	6456	1			T16	1		T17	561		T6	821
valid_sources[0x0a]	6318	1			T17	603		T6	763		T9	331
valid_sources[0x0b]	6283	1			T17	600		T6	706		T37	4
valid_sources[0x0c]	6996	1			T17	593		T6	786		T9	354
valid_sources[0x0d]	6059	1			T17	622		T6	750		T9	293
valid_sources[0x0e]	6084	1			T16	2		T38	1		T17	616
valid_sources[0x0f]	6314	1			T17	624		T6	785		T9	371
valid_sources[0x10]	6472	1			T18	1		T17	604		T6	770
valid_sources[0x11]	6796	1			T17	638		T6	754		T9	265
valid_sources[0x12]	6577	1			T17	568		T6	799		T9	345
valid_sources[0x13]	6103	1			T16	1		T17	605		T6	725
valid_sources[0x14]	6428	1			T38	1		T17	661		T166	2
valid_sources[0x15]	6434	1			T17	595		T6	798		T9	350
valid_sources[0x16]	5706	1			T17	586		T6	803		T9	269
valid_sources[0x17]	6576	1			T17	542		T6	771		T37	1
valid_sources[0x18]	7060	1			T17	557		T6	751		T39	5
valid_sources[0x19]	6105	1			T17	554		T6	782		T9	335
valid_sources[0x1a]	6359	1			T20	1		T17	674		T6	770
valid_sources[0x1b]	7102	1			T18	1		T17	594		T6	807
valid_sources[0x1c]	6278	1			T17	517		T6	708		T9	329
valid_sources[0x1d]	6427	1			T4	30		T18	1		T17	593
valid_sources[0x1e]	6349	1			T17	554		T6	801		T9	293
valid_sources[0x1f]	6314	1			T17	605		T6	791		T9	360
valid_sources[0x20]	6021	1			T17	650		T6	726		T9	306
valid_sources[0x21]	6974	1			T17	632		T6	803		T9	314
valid_sources[0x22]	6139	1			T17	620		T6	776		T9	243
valid_sources[0x23]	6913	1			T17	555		T6	806		T9	393
valid_sources[0x24]	6084	1			T17	612		T8	1		T6	780
valid_sources[0x25]	6537	1			T17	599		T74	1		T6	757
valid_sources[0x26]	6143	1			T38	1		T17	584		T6	734
valid_sources[0x27]	6581	1			T17	597		T166	1		T6	799
valid_sources[0x28]	6598	1			T17	567		T6	753		T9	337
valid_sources[0x29]	6527	1			T16	1		T17	548		T166	1
valid_sources[0x2a]	6471	1			T17	559		T6	741		T9	346
valid_sources[0x2b]	6218	1			T17	587		T6	767		T9	432
valid_sources[0x2c]	6446	1			T17	596		T6	787		T9	364
valid_sources[0x2d]	6858	1			T17	631		T6	772		T9	371
valid_sources[0x2e]	6364	1			T17	558		T6	784		T9	278
valid_sources[0x2f]	5720	1			T17	575		T6	743		T9	255
valid_sources[0x30]	6490	1			T17	600		T8	1		T6	757
valid_sources[0x31]	6427	1			T17	586		T8	1		T6	737
valid_sources[0x32]	6261	1			T17	511		T6	768		T39	5
valid_sources[0x33]	6258	1			T17	592		T6	800		T9	383
valid_sources[0x34]	6110	1			T17	574		T8	1		T74	1
valid_sources[0x35]	6229	1			T17	575		T6	766		T9	312
valid_sources[0x36]	6297	1			T17	557		T6	736		T9	334
valid_sources[0x37]	6011	1			T17	594		T6	775		T9	362
valid_sources[0x38]	6243	1			T17	541		T58	1		T6	753
valid_sources[0x39]	6428	1			T38	1		T17	575		T6	799
valid_sources[0x3a]	6582	1			T17	602		T6	837		T9	342
valid_sources[0x3b]	6319	1			T17	577		T6	768		T9	344
valid_sources[0x3c]	6502	1			T17	605		T6	807		T9	271
valid_sources[0x3d]	6098	1			T36	1		T17	535		T6	756
valid_sources[0x3e]	7278	1			T17	603		T8	2		T6	801
valid_sources[0x3f]	5786	1			T17	595		T166	2		T6	772
valid_sources[0x40]	6295	1			T17	591		T6	730		T9	300
valid_sources[0x41]	6528	1			T17	655		T6	758		T9	409
valid_sources[0x42]	6273	1			T17	608		T6	750		T9	321
valid_sources[0x43]	6671	1			T38	1		T17	649		T6	757
valid_sources[0x44]	5928	1			T17	600		T166	1		T6	751
valid_sources[0x45]	6623	1			T17	566		T6	799		T9	302
valid_sources[0x46]	6953	1			T5	2		T17	608		T6	768
valid_sources[0x47]	6337	1			T17	598		T127	2		T6	773
valid_sources[0x48]	5905	1			T36	4		T38	1		T17	584
valid_sources[0x49]	6189	1			T20	3		T17	587		T8	1
valid_sources[0x4a]	8227	1			T17	596		T6	806		T9	339
valid_sources[0x4b]	6267	1			T17	544		T6	728		T9	339
valid_sources[0x4c]	6178	1			T17	649		T166	1		T6	795
valid_sources[0x4d]	6472	1			T17	537		T6	800		T9	409
valid_sources[0x4e]	6145	1			T17	583		T6	783		T9	310
valid_sources[0x4f]	6269	1			T17	601		T6	794		T9	305
valid_sources[0x50]	6235	1			T17	574		T6	769		T9	390
valid_sources[0x51]	6159	1			T17	585		T6	742		T9	343
valid_sources[0x52]	6586	1			T38	1		T17	579		T166	1
valid_sources[0x53]	5916	1			T17	502		T6	792		T9	375
valid_sources[0x54]	6789	1			T24	16		T17	579		T6	762
valid_sources[0x55]	6921	1			T18	1		T17	580		T74	1
valid_sources[0x56]	6815	1			T17	637		T6	819		T9	367
valid_sources[0x57]	6951	1			T20	1		T17	604		T6	801
valid_sources[0x58]	6035	1			T38	1		T17	614		T6	753
valid_sources[0x59]	6253	1			T17	599		T6	812		T9	351
valid_sources[0x5a]	6745	1			T17	601		T6	725		T9	302
valid_sources[0x5b]	6040	1			T17	588		T6	750		T9	322
valid_sources[0x5c]	6202	1			T17	559		T6	759		T37	1
valid_sources[0x5d]	5895	1			T1	8		T17	554		T6	746
valid_sources[0x5e]	6486	1			T17	599		T6	784		T9	382
valid_sources[0x5f]	6430	1			T17	599		T6	779		T9	347
valid_sources[0x60]	6162	1			T17	583		T21	1		T6	772
valid_sources[0x61]	6208	1			T16	3		T38	1		T17	581
valid_sources[0x62]	6390	1			T17	612		T8	1		T6	778
valid_sources[0x63]	6108	1			T17	654		T6	757		T9	391
valid_sources[0x64]	6612	1			T17	615		T6	777		T9	340
valid_sources[0x65]	6485	1			T17	603		T6	799		T9	335
valid_sources[0x66]	6102	1			T17	586		T6	742		T9	406
valid_sources[0x67]	5655	1			T17	582		T6	790		T9	340
valid_sources[0x68]	6058	1			T17	566		T6	728		T9	334
valid_sources[0x69]	6622	1			T18	1		T17	568		T74	1
valid_sources[0x6a]	6459	1			T38	1		T17	553		T6	750
valid_sources[0x6b]	6452	1			T17	595		T6	760		T37	1
valid_sources[0x6c]	6423	1			T17	615		T6	762		T9	301
valid_sources[0x6d]	5903	1			T18	1		T17	557		T6	809
valid_sources[0x6e]	6216	1			T17	605		T6	721		T9	291
valid_sources[0x6f]	6479	1			T17	598		T166	1		T6	734
valid_sources[0x70]	8314	1			T17	522		T6	767		T9	435
valid_sources[0x71]	7080	1			T17	687		T21	1		T6	774
valid_sources[0x72]	7276	1			T17	570		T6	772		T9	368
valid_sources[0x73]	6881	1			T17	612		T58	1		T6	752
valid_sources[0x74]	6612	1			T17	553		T6	774		T37	2
valid_sources[0x75]	6293	1			T17	552		T21	2		T6	749
valid_sources[0x76]	7116	1			T18	1		T17	603		T6	791
valid_sources[0x77]	7161	1			T17	570		T6	792		T9	273
valid_sources[0x78]	6196	1			T17	553		T6	726		T9	345
valid_sources[0x79]	6970	1			T17	612		T6	704		T9	378
valid_sources[0x7a]	6065	1			T16	2		T17	661		T6	724
valid_sources[0x7b]	6240	1			T17	564		T6	751		T9	415
valid_sources[0x7c]	5951	1			T17	569		T6	726		T9	317
valid_sources[0x7d]	6420	1			T17	586		T6	747		T9	311
valid_sources[0x7e]	5997	1			T18	1		T17	622		T6	751
valid_sources[0x7f]	6564	1			T18	1		T17	562		T6	776
valid_sources[0x80]	6311	1			T17	559		T6	763		T9	293

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

392131

1

T1

2

T2

3

T24

1

values[0x0]

all_enables

biggest_size

293682

1

T2

2

T24

4

T4

6

values[0x1]

all_enables

biggest_size

292419

1

T1

1

T24

2

T4

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28397	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

621926

1

T1

6

T2

8

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	167550	1			T17	27478		T6	35532		T9	16676
values[0x0]	235137	1			T1	5		T2	3		T3	1
values[0x1]	247636	1			T1	1		T2	5		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15341	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

634982

1

T1

6

T2

8

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3005	1			T17	397		T6	712		T9	326
valid_sources[0x01]	2732	1			T17	426		T53	1		T167	1
valid_sources[0x02]	2460	1			T17	418		T6	502		T39	1
valid_sources[0x03]	2599	1			T17	457		T73	1		T6	455
valid_sources[0x04]	2263	1			T17	441		T6	601		T9	239
valid_sources[0x05]	2614	1			T46	1		T17	427		T73	1
valid_sources[0x06]	2483	1			T29	1		T17	416		T6	538
valid_sources[0x07]	2489	1			T17	414		T6	472		T9	260
valid_sources[0x08]	2671	1			T4	2		T17	453		T6	530
valid_sources[0x09]	2120	1			T17	417		T6	661		T9	224
valid_sources[0x0a]	2687	1			T20	1		T17	426		T6	572
valid_sources[0x0b]	3079	1			T3	1		T22	1		T17	430
valid_sources[0x0c]	2453	1			T17	445		T71	1		T6	622
valid_sources[0x0d]	2163	1			T49	1		T17	421		T6	584
valid_sources[0x0e]	2828	1			T17	441		T6	525		T168	1
valid_sources[0x0f]	2386	1			T17	386		T6	618		T62	1
valid_sources[0x10]	2513	1			T17	412		T6	593		T9	351
valid_sources[0x11]	2204	1			T17	482		T53	1		T6	551
valid_sources[0x12]	3041	1			T17	391		T59	3		T6	461
valid_sources[0x13]	3191	1			T4	1		T17	457		T6	596
valid_sources[0x14]	2645	1			T24	2		T17	427		T169	1
valid_sources[0x15]	2650	1			T17	406		T6	531		T13	1
valid_sources[0x16]	1969	1			T2	1		T17	429		T6	496
valid_sources[0x17]	2509	1			T28	2		T17	395		T6	510
valid_sources[0x18]	2501	1			T17	424		T6	565		T9	201
valid_sources[0x19]	2184	1			T10	1		T22	1		T17	425
valid_sources[0x1a]	2392	1			T17	410		T6	458		T9	313
valid_sources[0x1b]	2085	1			T17	460		T6	546		T9	232
valid_sources[0x1c]	2187	1			T22	4		T17	474		T6	578
valid_sources[0x1d]	2500	1			T17	440		T6	423		T9	184
valid_sources[0x1e]	2841	1			T2	1		T17	435		T127	1
valid_sources[0x1f]	2282	1			T17	420		T6	669		T9	300
valid_sources[0x20]	2242	1			T17	424		T6	584		T9	219
valid_sources[0x21]	2162	1			T17	424		T73	1		T6	617
valid_sources[0x22]	2475	1			T20	2		T17	457		T8	1
valid_sources[0x23]	3166	1			T18	1		T17	474		T6	503
valid_sources[0x24]	2733	1			T17	380		T6	562		T62	2
valid_sources[0x25]	2387	1			T17	395		T53	1		T6	544
valid_sources[0x26]	2927	1			T17	437		T6	682		T9	276
valid_sources[0x27]	2213	1			T17	444		T167	1		T6	591
valid_sources[0x28]	1921	1			T17	365		T73	1		T6	622
valid_sources[0x29]	2786	1			T17	429		T6	424		T170	1
valid_sources[0x2a]	2772	1			T17	450		T6	562		T9	239
valid_sources[0x2b]	2511	1			T17	428		T6	596		T9	254
valid_sources[0x2c]	2742	1			T17	477		T73	1		T6	467
valid_sources[0x2d]	2551	1			T17	394		T6	603		T9	280
valid_sources[0x2e]	2610	1			T17	405		T6	545		T9	265
valid_sources[0x2f]	2513	1			T17	451		T72	13		T6	719
valid_sources[0x30]	2640	1			T17	405		T6	516		T9	201
valid_sources[0x31]	2585	1			T17	425		T8	1		T6	419
valid_sources[0x32]	2844	1			T17	429		T6	579		T9	311
valid_sources[0x33]	3180	1			T17	429		T6	516		T9	224
valid_sources[0x34]	2511	1			T85	1		T17	389		T169	2
valid_sources[0x35]	1834	1			T17	377		T6	460		T9	249
valid_sources[0x36]	2300	1			T17	422		T6	538		T37	1
valid_sources[0x37]	2155	1			T110	6		T17	365		T6	430
valid_sources[0x38]	2436	1			T17	422		T6	560		T9	276
valid_sources[0x39]	2738	1			T17	420		T73	1		T6	512
valid_sources[0x3a]	2087	1			T17	418		T6	367		T9	248
valid_sources[0x3b]	2674	1			T17	417		T6	516		T9	253
valid_sources[0x3c]	2178	1			T17	411		T6	535		T9	226
valid_sources[0x3d]	2915	1			T28	1		T17	429		T6	519
valid_sources[0x3e]	2502	1			T24	2		T17	445		T6	514
valid_sources[0x3f]	3088	1			T17	490		T73	1		T21	1
valid_sources[0x40]	2419	1			T2	1		T17	435		T6	584
valid_sources[0x41]	2759	1			T17	394		T6	805		T9	223
valid_sources[0x42]	2392	1			T29	2		T17	406		T6	530
valid_sources[0x43]	2992	1			T30	9		T4	2		T17	412
valid_sources[0x44]	2849	1			T17	388		T6	429		T171	1
valid_sources[0x45]	2391	1			T17	455		T6	660		T9	280
valid_sources[0x46]	2487	1			T17	468		T6	489		T37	1
valid_sources[0x47]	2647	1			T2	1		T20	1		T17	435
valid_sources[0x48]	2543	1			T17	448		T6	662		T9	262
valid_sources[0x49]	2433	1			T17	432		T6	376		T39	1
valid_sources[0x4a]	2975	1			T18	2		T17	427		T6	549
valid_sources[0x4b]	2448	1			T2	1		T17	428		T6	564
valid_sources[0x4c]	2264	1			T17	416		T6	554		T9	324
valid_sources[0x4d]	2473	1			T18	1		T17	430		T6	555
valid_sources[0x4e]	2418	1			T17	419		T6	419		T9	279
valid_sources[0x4f]	2733	1			T17	405		T74	9		T6	496
valid_sources[0x50]	2306	1			T17	416		T73	1		T6	599
valid_sources[0x51]	3017	1			T2	1		T17	436		T6	567
valid_sources[0x52]	2565	1			T17	473		T6	403		T9	248
valid_sources[0x53]	2105	1			T17	423		T6	477		T9	269
valid_sources[0x54]	2639	1			T17	459		T53	1		T6	494
valid_sources[0x55]	1950	1			T17	446		T6	442		T9	259
valid_sources[0x56]	2876	1			T17	436		T53	1		T6	451
valid_sources[0x57]	3310	1			T57	1		T20	1		T17	464
valid_sources[0x58]	3305	1			T17	424		T6	557		T9	276
valid_sources[0x59]	2402	1			T17	419		T6	546		T9	213
valid_sources[0x5a]	3071	1			T17	471		T6	534		T9	191
valid_sources[0x5b]	2837	1			T17	427		T6	541		T9	196
valid_sources[0x5c]	2638	1			T17	401		T6	503		T9	269
valid_sources[0x5d]	2383	1			T17	412		T21	1		T6	642
valid_sources[0x5e]	2520	1			T57	6		T110	2		T17	375
valid_sources[0x5f]	1896	1			T17	459		T6	535		T9	246
valid_sources[0x60]	2659	1			T3	1		T17	417		T167	1
valid_sources[0x61]	2409	1			T17	420		T6	478		T9	244
valid_sources[0x62]	2294	1			T17	415		T73	2		T6	633
valid_sources[0x63]	2614	1			T17	425		T6	672		T9	287
valid_sources[0x64]	2986	1			T17	445		T6	638		T124	1
valid_sources[0x65]	2509	1			T17	411		T73	1		T6	647
valid_sources[0x66]	2219	1			T17	492		T6	570		T9	218
valid_sources[0x67]	2233	1			T17	404		T6	539		T134	1
valid_sources[0x68]	2968	1			T17	415		T58	8		T6	751
valid_sources[0x69]	2217	1			T17	456		T6	475		T172	1
valid_sources[0x6a]	2698	1			T17	409		T6	620		T124	1
valid_sources[0x6b]	2464	1			T16	7		T17	439		T166	1
valid_sources[0x6c]	2253	1			T17	443		T6	566		T9	314
valid_sources[0x6d]	2240	1			T17	416		T6	551		T9	216
valid_sources[0x6e]	2512	1			T17	398		T6	683		T9	279
valid_sources[0x6f]	1897	1			T3	1		T17	410		T6	540
valid_sources[0x70]	2350	1			T17	440		T167	2		T6	457
valid_sources[0x71]	2191	1			T17	433		T21	1		T6	374
valid_sources[0x72]	2682	1			T17	389		T6	425		T9	276
valid_sources[0x73]	2078	1			T17	424		T6	433		T9	242
valid_sources[0x74]	2424	1			T17	440		T6	462		T9	243
valid_sources[0x75]	2697	1			T17	402		T6	566		T9	280
valid_sources[0x76]	2989	1			T17	415		T6	559		T9	287
valid_sources[0x77]	3262	1			T36	1		T17	407		T6	638
valid_sources[0x78]	2482	1			T17	440		T6	614		T9	207
valid_sources[0x79]	2987	1			T17	432		T6	623		T9	281
valid_sources[0x7a]	2311	1			T17	429		T6	599		T9	245
valid_sources[0x7b]	1853	1			T11	1		T17	410		T6	382
valid_sources[0x7c]	2320	1			T17	416		T73	1		T6	380
valid_sources[0x7d]	2135	1			T17	387		T6	472		T9	251
valid_sources[0x7e]	2458	1			T17	430		T6	524		T9	285
valid_sources[0x7f]	2481	1			T17	433		T6	489		T62	1
valid_sources[0x80]	3020	1			T17	415		T6	550		T9	234

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

156719

1

T17

26109

T6

33611

T9

15762

values[0x0]

all_enables

biggest_size

232547

1

T1

5

T2

3

T3

1

values[0x1]

all_enables

biggest_size

232660

1

T1

1

T2

5

T3

5