Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3527929

1

T1

5

T2

14

T3

1

full_word

1077197

1

T1

3

T2

5

T24

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4604806	1			T1	8		T2	19		T3	1
auto[TlIntgErrCmd]	121	1			T67	6		T68	4		T111	3
auto[TlIntgErrData]	94	1			T67	3		T68	7		T111	5
auto[TlIntgErrBoth]	105	1			T67	1		T68	9		T111	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721714

1

T1

3

T2

6

T24

1

auto[1]

3883412

1

T1

5

T2

13

T3

1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	317586	1			T1	1		T2	3		T18	1
auto[TlIntgErrNone]	partial	auto[1]	3210049	1			T1	4		T2	11		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	403975	1			T1	2		T2	3		T24	1
auto[TlIntgErrNone]	full_word	auto[1]	673196	1			T1	1		T2	2		T24	6
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T67	2		T68	1		T111	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T67	2		T68	3		T111	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T67	1		T151	1		T157	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T67	1		T111	1		T151	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T68	2		T111	3		T151	3
auto[TlIntgErrData]	partial	auto[1]	47	1			T67	3		T68	5		T111	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T158	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T154	1		T159	2		T156	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T67	1		T68	4		T111	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T68	5		T111	1		T151	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T154	1		T155	1		T160	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T157	1		T161	1		T162	1