Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	141451833	849113	0	0
late_debug_enable_rd_A	141451833	71481	0	0
late_debug_enable_regwen_rd_A	141451833	64449	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141451833	849113	0	0
T6	0	193443	0	0
T8	195141	0	0	0
T9	0	86606	0	0
T17	448129	142151	0	0
T26	94923	0	0	0
T40	0	114884	0	0
T47	42228	0	0	0
T48	0	42303	0	0
T53	2957	0	0	0
T59	21155	0	0	0
T64	0	73254	0	0
T65	0	121145	0	0
T66	0	186	0	0
T67	0	3	0	0
T68	0	6	0	0
T71	53988	0	0	0
T72	1534	0	0	0
T73	3809	0	0	0
T74	51969	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141451833	71481	0	0
T9	487187	29487	0	0
T64	0	24833	0	0
T67	0	55	0	0
T70	0	35	0	0
T78	0	13	0	0
T82	0	407	0	0
T83	0	136	0	0
T101	0	947	0	0
T111	0	44	0	0
T112	0	8	0	0
T113	67446	0	0	0
T114	1958	0	0	0
T115	17479	0	0	0
T116	145257	0	0	0
T117	4285	0	0	0
T118	9823	0	0	0
T119	5821	0	0	0
T120	4441	0	0	0
T121	3219	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141451833	64449	0	0
T9	487187	25998	0	0
T64	0	21401	0	0
T67	0	55	0	0
T70	0	23	0	0
T78	0	10	0	0
T82	0	442	0	0
T83	0	124	0	0
T84	0	1985	0	0
T111	0	32	0	0
T112	0	20	0	0
T113	67446	0	0	0
T114	1958	0	0	0
T115	17479	0	0	0
T116	145257	0	0	0
T117	4285	0	0	0
T118	9823	0	0	0
T119	5821	0	0	0
T120	4441	0	0	0
T121	3219	0	0	0