Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
71947915 |
71896596 |
0 |
0 |
T1 |
33964 |
33913 |
0 |
0 |
T2 |
171650 |
171325 |
0 |
0 |
T3 |
48221 |
48086 |
0 |
0 |
T5 |
16064 |
16014 |
0 |
0 |
T10 |
97573 |
97516 |
0 |
0 |
T11 |
216299 |
216239 |
0 |
0 |
T28 |
8499 |
8447 |
0 |
0 |
T29 |
3097 |
3022 |
0 |
0 |
T30 |
4100 |
4050 |
0 |
0 |
T31 |
14178 |
13403 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
71947915 |
71896596 |
0 |
0 |
T1 |
33964 |
33913 |
0 |
0 |
T2 |
171650 |
171325 |
0 |
0 |
T3 |
48221 |
48086 |
0 |
0 |
T5 |
16064 |
16014 |
0 |
0 |
T10 |
97573 |
97516 |
0 |
0 |
T11 |
216299 |
216239 |
0 |
0 |
T28 |
8499 |
8447 |
0 |
0 |
T29 |
3097 |
3022 |
0 |
0 |
T30 |
4100 |
4050 |
0 |
0 |
T31 |
14178 |
13403 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
71947915 |
71896596 |
0 |
0 |
T1 |
33964 |
33913 |
0 |
0 |
T2 |
171650 |
171325 |
0 |
0 |
T3 |
48221 |
48086 |
0 |
0 |
T5 |
16064 |
16014 |
0 |
0 |
T10 |
97573 |
97516 |
0 |
0 |
T11 |
216299 |
216239 |
0 |
0 |
T28 |
8499 |
8447 |
0 |
0 |
T29 |
3097 |
3022 |
0 |
0 |
T30 |
4100 |
4050 |
0 |
0 |
T31 |
14178 |
13403 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
71947915 |
71896596 |
0 |
0 |
T1 |
33964 |
33913 |
0 |
0 |
T2 |
171650 |
171325 |
0 |
0 |
T3 |
48221 |
48086 |
0 |
0 |
T5 |
16064 |
16014 |
0 |
0 |
T10 |
97573 |
97516 |
0 |
0 |
T11 |
216299 |
216239 |
0 |
0 |
T28 |
8499 |
8447 |
0 |
0 |
T29 |
3097 |
3022 |
0 |
0 |
T30 |
4100 |
4050 |
0 |
0 |
T31 |
14178 |
13403 |
0 |
0 |