Module Definition
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Module : tlul_adapter_reg
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.91 98.96 95.05 97.62 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i_tlul_adapter_reg 96.90 97.92 94.44 95.24 100.00
tb.dut.u_reg_regs.u_reg_if 98.91 100.00 95.65 100.00 100.00



Module Instance : tb.dut.i_tlul_adapter_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 97.92 94.44 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.10 99.00 96.63 93.33 96.55 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 97.78 100.00 93.33 100.00
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00



Module Instance : tb.dut.u_reg_regs.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.91 100.00 95.65 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.67 97.14 97.53 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00

Line Coverage for Module : tlul_adapter_reg ( parameter CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,RegAw=4,RegDw=32,AccessLatency=0,RegBw=4,IW=8,SZW=2 )
Line Coverage for Module self-instances :
SCORELINE
98.91 100.00
tb.dut.u_reg_regs.u_reg_if

Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Line Coverage for Module : tlul_adapter_reg ( parameter CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,RegAw=12,RegDw=32,AccessLatency=1,RegBw=4,IW=8,SZW=2 )
Line Coverage for Module self-instances :
SCORELINE
96.90 97.92
tb.dut.i_tlul_adapter_reg

Line No.TotalCoveredPercent
TOTAL484797.92
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS1161111100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN15411100.00
ALWAYS1864375.00
CONT_ASSIGN19211100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
122 1 1
123 1 1
125 1 1
126 1 1
129 1 1
130 1 1
134 1 1
137 1 1
154 1 1
186 1 1
187 1 1
188 1 1
189 0 1
MISSING_ELSE
192 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Module : tlul_adapter_reg ( parameter CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,RegAw=4,RegDw=32,AccessLatency=0,RegBw=4,IW=8,SZW=2 )
Cond Coverage for Module self-instances :
SCORECOND
98.91 95.65
tb.dut.u_reg_regs.u_reg_if

TotalCoveredPercent
Conditions464495.65
Logical464495.65
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T6,T9
11CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT2,T28,T30
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT2,T28,T30
10CoveredT1,T2,T3
11CoveredT17,T6,T9

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T28,T30

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T6,T9
11CoveredT1,T2,T3

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T6,T9
11CoveredT17,T6,T9

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T6,T9

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT17,T6,T9
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT17,T6,T9
001CoveredT1,T2,T3
010CoveredT17,T6,T9
100CoveredT17,T6,T9

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T6,T9
10CoveredT17,T6,T9

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Unreachable
00010Not Covered
00100CoveredT2,T28,T30
01000Not Covered
10000CoveredT17,T6,T9

Cond Coverage for Module : tlul_adapter_reg ( parameter CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,RegAw=12,RegDw=32,AccessLatency=1,RegBw=4,IW=8,SZW=2 )
Cond Coverage for Module self-instances :
SCORECOND
96.90 94.44
tb.dut.i_tlul_adapter_reg

TotalCoveredPercent
Conditions545194.44
Logical545194.44
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T24
11CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T31
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T31

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T24

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T6,T9
11CoveredT1,T2,T3

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T6,T9
11CoveredT1,T2,T24

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T24

 LINE       134
 EXPRESSION ((error_i || error_q || gen_access_latency1.wr_req_q) ? '1 : (gen_access_latency1.rd_req_q ? rdata_i : rdata_q))
             --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       134
 SUB-EXPRESSION (error_i || error_q || gen_access_latency1.wr_req_q)
                 ---1---    ---2---    --------------3-------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT17,T6,T9
100CoveredT17,T6,T9

 LINE       134
 SUB-EXPRESSION (gen_access_latency1.rd_req_q ? rdata_i : rdata_q)
                 --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T24

 LINE       137
 EXPRESSION ((gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q) ? (error_q || error_i) : error_q)
             -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q)
                 --------------1-------------    --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T24

 LINE       137
 SUB-EXPRESSION (error_q || error_i)
                 ---1---    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T6,T9
10CoveredT17,T6,T9

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Not Covered
00100CoveredT3,T31,T11
01000Not Covered
10000CoveredT17,T6,T9

Branch Coverage for Module : tlul_adapter_reg ( parameter CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,RegAw=4,RegDw=32,AccessLatency=0,RegBw=4,IW=8,SZW=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
98.91 100.00
tb.dut.u_reg_regs.u_reg_if

Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T17,T6,T9
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T17,T6,T9
0 0 - Covered T1,T2,T3


Branch Coverage for Module : tlul_adapter_reg ( parameter CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,RegAw=12,RegDw=32,AccessLatency=1,RegBw=4,IW=8,SZW=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
96.90 95.24
tb.dut.i_tlul_adapter_reg

Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 134 3 3 100.00
TERNARY 137 2 2 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 116 3 3 100.00
IF 186 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 134 (((error_i || error_q) || gen_access_latency1.wr_req_q)) ? -2-: 134 (gen_access_latency1.rd_req_q) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T24
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 137 ((gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T24
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 116 if ((!rst_ni)) -2-: 125 if (a_ack)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 186 if ((!rst_ni)) -2-: 188 if (intg_error)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 710 710 0 0
MatchedWidthAssert 710 710 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 710 710 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T5 2 2 0 0
T10 2 2 0 0
T11 2 2 0 0
T28 2 2 0 0
T29 2 2 0 0
T30 2 2 0 0
T31 2 2 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 710 710 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T5 2 2 0 0
T10 2 2 0 0
T11 2 2 0 0
T28 2 2 0 0
T29 2 2 0 0
T30 2 2 0 0
T31 2 2 0 0

Line Coverage for Instance : tb.dut.i_tlul_adapter_reg
Line No.TotalCoveredPercent
TOTAL484797.92
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS1161111100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN15411100.00
ALWAYS1864375.00
CONT_ASSIGN19211100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
122 1 1
123 1 1
125 1 1
126 1 1
129 1 1
130 1 1
134 1 1
137 1 1
154 1 1
186 1 1
187 1 1
188 1 1
189 0 1
MISSING_ELSE
192 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.i_tlul_adapter_reg
TotalCoveredPercent
Conditions545194.44
Logical545194.44
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T24
11CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T31
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T31

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T24

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T6,T9
11CoveredT1,T2,T3

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T6,T9
11CoveredT1,T2,T24

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T24

 LINE       134
 EXPRESSION ((error_i || error_q || gen_access_latency1.wr_req_q) ? '1 : (gen_access_latency1.rd_req_q ? rdata_i : rdata_q))
             --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       134
 SUB-EXPRESSION (error_i || error_q || gen_access_latency1.wr_req_q)
                 ---1---    ---2---    --------------3-------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT17,T6,T9
100CoveredT17,T6,T9

 LINE       134
 SUB-EXPRESSION (gen_access_latency1.rd_req_q ? rdata_i : rdata_q)
                 --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T24

 LINE       137
 EXPRESSION ((gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q) ? (error_q || error_i) : error_q)
             -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q)
                 --------------1-------------    --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T24

 LINE       137
 SUB-EXPRESSION (error_q || error_i)
                 ---1---    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T6,T9
10CoveredT17,T6,T9

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Not Covered
00100CoveredT3,T31,T11
01000Not Covered
10000CoveredT17,T6,T9

Branch Coverage for Instance : tb.dut.i_tlul_adapter_reg
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 134 3 3 100.00
TERNARY 137 2 2 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 116 3 3 100.00
IF 186 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 134 (((error_i || error_q) || gen_access_latency1.wr_req_q)) ? -2-: 134 (gen_access_latency1.rd_req_q) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T24
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 137 ((gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T24
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 116 if ((!rst_ni)) -2-: 125 if (a_ack)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 186 if ((!rst_ni)) -2-: 188 if (intg_error)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i_tlul_adapter_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 245 245 0 0
MatchedWidthAssert 245 245 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
TotalCoveredPercent
Conditions464495.65
Logical464495.65
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T6,T9
11CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT2,T28,T30
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT2,T28,T30
10CoveredT1,T2,T3
11CoveredT17,T6,T9

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T28,T30

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T6,T9
11CoveredT1,T2,T3

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T6,T9
11CoveredT17,T6,T9

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T6,T9

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT17,T6,T9
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT17,T6,T9
001CoveredT1,T2,T3
010CoveredT17,T6,T9
100CoveredT17,T6,T9

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T6,T9
10CoveredT17,T6,T9

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Unreachable
00010Not Covered
00100CoveredT2,T28,T30
01000Not Covered
10000CoveredT17,T6,T9

Branch Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T17,T6,T9
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T17,T6,T9
0 0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 465 465 0 0
MatchedWidthAssert 465 465 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 465 465 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 465 465 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%