Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 15777929 15776509 0 0
selKnown1 82069531 82068111 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 15777929 15776509 0 0
T1 13821 13818 0 0
T2 17945 17941 0 0
T3 19944 19940 0 0
T4 0 8 0 0
T5 2020 2016 0 0
T10 36221 36217 0 0
T11 10409 10405 0 0
T16 0 5 0 0
T18 0 6 0 0
T22 0 18 0 0
T24 7 12 0 0
T28 379 375 0 0
T29 607 603 0 0
T30 371 367 0 0
T31 3328 3324 0 0
T45 0 2 0 0
T46 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 82069531 82068111 0 0
T1 40873 40871 0 0
T2 180627 180623 0 0
T3 58194 58190 0 0
T4 0 8 0 0
T5 17075 17071 0 0
T10 115684 115680 0 0
T11 221504 221500 0 0
T16 0 10 0 0
T18 0 6 0 0
T20 0 8 0 0
T22 0 18 0 0
T24 12 10 0 0
T28 8689 8685 0 0
T29 3401 3397 0 0
T30 4286 4282 0 0
T31 15853 15849 0 0
T45 0 2 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 5655914 5655669 0 0
selKnown1 71947915 71947670 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 5655914 5655669 0 0
T1 6909 6908 0 0
T2 8967 8966 0 0
T3 9969 9968 0 0
T5 1009 1008 0 0
T10 18109 18108 0 0
T11 5203 5202 0 0
T28 188 187 0 0
T29 302 301 0 0
T30 184 183 0 0
T31 1653 1652 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71947670 0 0
T1 33964 33963 0 0
T2 171650 171649 0 0
T3 48221 48220 0 0
T5 16064 16063 0 0
T10 97573 97572 0 0
T11 216299 216298 0 0
T28 8499 8498 0 0
T29 3097 3096 0 0
T30 4100 4099 0 0
T31 14178 14177 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 748 503 0 0
selKnown1 689 444 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 748 503 0 0
T2 5 4 0 0
T3 2 1 0 0
T4 0 4 0 0
T5 1 0 0 0
T10 1 0 0 0
T11 1 0 0 0
T16 0 5 0 0
T18 0 3 0 0
T22 0 9 0 0
T24 7 6 0 0
T28 1 0 0 0
T29 1 0 0 0
T30 1 0 0 0
T31 11 10 0 0
T45 0 1 0 0
T46 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 689 444 0 0
T2 5 4 0 0
T3 2 1 0 0
T4 0 4 0 0
T5 1 0 0 0
T10 1 0 0 0
T11 1 0 0 0
T16 0 5 0 0
T18 0 3 0 0
T20 0 4 0 0
T22 0 9 0 0
T24 6 5 0 0
T28 1 0 0 0
T29 1 0 0 0
T30 1 0 0 0
T31 11 10 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10119313 10118848 0 0
selKnown1 10119081 10118616 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10119313 10118848 0 0
T1 6910 6909 0 0
T2 8968 8967 0 0
T3 9970 9969 0 0
T5 1009 1008 0 0
T10 18110 18109 0 0
T11 5204 5203 0 0
T28 189 188 0 0
T29 303 302 0 0
T30 185 184 0 0
T31 1653 1652 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 10119081 10118616 0 0
T1 6909 6908 0 0
T2 8967 8966 0 0
T3 9969 9968 0 0
T5 1009 1008 0 0
T10 18109 18108 0 0
T11 5203 5202 0 0
T28 188 187 0 0
T29 302 301 0 0
T30 184 183 0 0
T31 1653 1652 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1954 1489 0 0
selKnown1 1846 1381 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1954 1489 0 0
T1 2 1 0 0
T2 5 4 0 0
T3 3 2 0 0
T4 0 4 0 0
T5 1 0 0 0
T10 1 0 0 0
T11 1 0 0 0
T18 0 3 0 0
T22 0 9 0 0
T24 0 6 0 0
T28 1 0 0 0
T29 1 0 0 0
T30 1 0 0 0
T31 11 10 0 0
T45 0 1 0 0
T46 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1846 1381 0 0
T2 5 4 0 0
T3 2 1 0 0
T4 0 4 0 0
T5 1 0 0 0
T10 1 0 0 0
T11 1 0 0 0
T16 0 5 0 0
T18 0 3 0 0
T20 0 4 0 0
T22 0 9 0 0
T24 6 5 0 0
T28 1 0 0 0
T29 1 0 0 0
T30 1 0 0 0
T31 11 10 0 0
T45 0 1 0 0

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