Module Definition
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Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_en_sync_copies

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_pm_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.13 86.27 72.22 57.14 75.00 50.00 u_tlul_lc_gate_sba


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.09 100.00 88.89 85.71 95.83 50.00 u_tlul_lc_gate_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_hw_debug_en

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_dft_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_lc_en_sync_copies

Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 5 5


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_pm_en_sync

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1470 1470 0 0
OutputsKnown_A 431687490 431379576 0 0
gen_flops.OutputDelay_A 215843745 215683587 0 2205
gen_no_flops.OutputDelay_A 215843745 215689788 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1470 1470 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T5 6 6 0 0
T10 6 6 0 0
T11 6 6 0 0
T28 6 6 0 0
T29 6 6 0 0
T30 6 6 0 0
T31 6 6 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431687490 431379576 0 0
T1 203784 203478 0 0
T2 1029900 1027950 0 0
T3 289326 288516 0 0
T5 96384 96084 0 0
T10 585438 585096 0 0
T11 1297794 1297434 0 0
T28 50994 50682 0 0
T29 18582 18132 0 0
T30 24600 24300 0 0
T31 85068 80418 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 215843745 215683587 0 2205
T1 101892 101730 0 9
T2 514950 513930 0 9
T3 144663 144240 0 9
T5 48192 48033 0 9
T10 292719 292539 0 9
T11 648897 648708 0 9
T28 25497 25332 0 9
T29 9291 9057 0 9
T30 12300 12141 0 9
T31 42534 40110 0 9

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 215843745 215689788 0 0
T1 101892 101739 0 0
T2 514950 513975 0 0
T3 144663 144258 0 0
T5 48192 48042 0 0
T10 292719 292548 0 0
T11 648897 648717 0 0
T28 25497 25341 0 0
T29 9291 9066 0 0
T30 12300 12150 0 0
T31 42534 40209 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 71947915 71896596 0 0
gen_flops.OutputDelay_A 71947915 71894529 0 735


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71896596 0 0
T1 33964 33913 0 0
T2 171650 171325 0 0
T3 48221 48086 0 0
T5 16064 16014 0 0
T10 97573 97516 0 0
T11 216299 216239 0 0
T28 8499 8447 0 0
T29 3097 3022 0 0
T30 4100 4050 0 0
T31 14178 13403 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71894529 0 735
T1 33964 33910 0 3
T2 171650 171310 0 3
T3 48221 48080 0 3
T5 16064 16011 0 3
T10 97573 97513 0 3
T11 216299 216236 0 3
T28 8499 8444 0 3
T29 3097 3019 0 3
T30 4100 4047 0 3
T31 14178 13370 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 71947915 71896596 0 0
gen_flops.OutputDelay_A 71947915 71894529 0 735


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71896596 0 0
T1 33964 33913 0 0
T2 171650 171325 0 0
T3 48221 48086 0 0
T5 16064 16014 0 0
T10 97573 97516 0 0
T11 216299 216239 0 0
T28 8499 8447 0 0
T29 3097 3022 0 0
T30 4100 4050 0 0
T31 14178 13403 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71894529 0 735
T1 33964 33910 0 3
T2 171650 171310 0 3
T3 48221 48080 0 3
T5 16064 16011 0 3
T10 97573 97513 0 3
T11 216299 216236 0 3
T28 8499 8444 0 3
T29 3097 3019 0 3
T30 4100 4047 0 3
T31 14178 13370 0 3

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 5 5


Assert Coverage for Instance : tb.dut.u_lc_en_sync_copies
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 71947915 71896596 0 0
gen_no_flops.OutputDelay_A 71947915 71896596 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71896596 0 0
T1 33964 33913 0 0
T2 171650 171325 0 0
T3 48221 48086 0 0
T5 16064 16014 0 0
T10 97573 97516 0 0
T11 216299 216239 0 0
T28 8499 8447 0 0
T29 3097 3022 0 0
T30 4100 4050 0 0
T31 14178 13403 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71896596 0 0
T1 33964 33913 0 0
T2 171650 171325 0 0
T3 48221 48086 0 0
T5 16064 16014 0 0
T10 97573 97516 0 0
T11 216299 216239 0 0
T28 8499 8447 0 0
T29 3097 3022 0 0
T30 4100 4050 0 0
T31 14178 13403 0 0

Line Coverage for Instance : tb.dut.u_pm_en_sync
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Assert Coverage for Instance : tb.dut.u_pm_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 71947915 71896596 0 0
gen_flops.OutputDelay_A 71947915 71894529 0 735


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71896596 0 0
T1 33964 33913 0 0
T2 171650 171325 0 0
T3 48221 48086 0 0
T5 16064 16014 0 0
T10 97573 97516 0 0
T11 216299 216239 0 0
T28 8499 8447 0 0
T29 3097 3022 0 0
T30 4100 4050 0 0
T31 14178 13403 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71894529 0 735
T1 33964 33910 0 3
T2 171650 171310 0 3
T3 48221 48080 0 3
T5 16064 16011 0 3
T10 97573 97513 0 3
T11 216299 216236 0 3
T28 8499 8444 0 3
T29 3097 3019 0 3
T30 4100 4047 0 3
T31 14178 13370 0 3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 71947915 71896596 0 0
gen_no_flops.OutputDelay_A 71947915 71896596 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71896596 0 0
T1 33964 33913 0 0
T2 171650 171325 0 0
T3 48221 48086 0 0
T5 16064 16014 0 0
T10 97573 97516 0 0
T11 216299 216239 0 0
T28 8499 8447 0 0
T29 3097 3022 0 0
T30 4100 4050 0 0
T31 14178 13403 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71896596 0 0
T1 33964 33913 0 0
T2 171650 171325 0 0
T3 48221 48086 0 0
T5 16064 16014 0 0
T10 97573 97516 0 0
T11 216299 216239 0 0
T28 8499 8447 0 0
T29 3097 3022 0 0
T30 4100 4050 0 0
T31 14178 13403 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 71947915 71896596 0 0
gen_no_flops.OutputDelay_A 71947915 71896596 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71896596 0 0
T1 33964 33913 0 0
T2 171650 171325 0 0
T3 48221 48086 0 0
T5 16064 16014 0 0
T10 97573 97516 0 0
T11 216299 216239 0 0
T28 8499 8447 0 0
T29 3097 3022 0 0
T30 4100 4050 0 0
T31 14178 13403 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 71947915 71896596 0 0
T1 33964 33913 0 0
T2 171650 171325 0 0
T3 48221 48086 0 0
T5 16064 16014 0 0
T10 97573 97516 0 0
T11 216299 216239 0 0
T28 8499 8447 0 0
T29 3097 3022 0 0
T30 4100 4050 0 0
T31 14178 13403 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%