SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 71947915 | 71896596 | 0 | 0 |
gen_no_flops.OutputDelay_A | 71947915 | 71896596 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 71947915 | 71896596 | 0 | 0 |
T1 | 33964 | 33913 | 0 | 0 |
T2 | 171650 | 171325 | 0 | 0 |
T3 | 48221 | 48086 | 0 | 0 |
T5 | 16064 | 16014 | 0 | 0 |
T10 | 97573 | 97516 | 0 | 0 |
T11 | 216299 | 216239 | 0 | 0 |
T28 | 8499 | 8447 | 0 | 0 |
T29 | 3097 | 3022 | 0 | 0 |
T30 | 4100 | 4050 | 0 | 0 |
T31 | 14178 | 13403 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 71947915 | 71896596 | 0 | 0 |
T1 | 33964 | 33913 | 0 | 0 |
T2 | 171650 | 171325 | 0 | 0 |
T3 | 48221 | 48086 | 0 | 0 |
T5 | 16064 | 16014 | 0 | 0 |
T10 | 97573 | 97516 | 0 | 0 |
T11 | 216299 | 216239 | 0 | 0 |
T28 | 8499 | 8447 | 0 | 0 |
T29 | 3097 | 3022 | 0 | 0 |
T30 | 4100 | 4050 | 0 | 0 |
T31 | 14178 | 13403 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |