SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 3462262 | 1 | T2 | 1 | T4 | 1 | T5 | 8 | ||||
auto[1] | 1198277 | 1 | T38 | 80 | T8 | 33827 | T39 | 80 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4660307 | 1 | T2 | 1 | T4 | 1 | T5 | 8 | ||||
values[1] | 24 | 1 | T130 | 2 | T131 | 2 | T132 | 1 | ||||
values[2] | 5 | 1 | T156 | 1 | T157 | 1 | T158 | 1 | ||||
values[3] | 115 | 1 | T130 | 3 | T131 | 5 | T132 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4660330 | 1 | T2 | 1 | T4 | 1 | T5 | 8 | ||||
values[1] | 16 | 1 | T130 | 1 | T132 | 1 | T128 | 1 | ||||
values[2] | 9 | 1 | T131 | 1 | T128 | 1 | T159 | 1 | ||||
values[3] | 112 | 1 | T130 | 3 | T131 | 4 | T132 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4660209 | 1 | T2 | 1 | T4 | 1 | T5 | 8 | ||||
auto[TlIntgErrCmd] | 121 | 1 | T130 | 3 | T131 | 8 | T132 | 9 | ||||
auto[TlIntgErrData] | 98 | 1 | T130 | 2 | T131 | 7 | T132 | 4 | ||||
auto[TlIntgErrBoth] | 111 | 1 | T130 | 5 | T131 | 5 | T132 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 1843391 | 0 | T1 | 1 | T7 | 1 | T2 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1843167 | 1 | T1 | 1 | T7 | 1 | T2 | 1 | ||||
values[1] | 28 | 1 | T131 | 1 | T132 | 1 | T127 | 1 | ||||
values[2] | 3 | 1 | T131 | 1 | T159 | 1 | T160 | 1 | ||||
values[3] | 120 | 1 | T130 | 4 | T131 | 7 | T132 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1843174 | 1 | T1 | 1 | T7 | 1 | T2 | 1 | ||||
values[1] | 19 | 1 | T130 | 1 | T132 | 3 | T127 | 1 | ||||
values[2] | 11 | 1 | T131 | 2 | T132 | 1 | T128 | 2 | ||||
values[3] | 116 | 1 | T130 | 4 | T131 | 4 | T132 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1843061 | 1 | T1 | 1 | T7 | 1 | T2 | 1 | ||||
auto[TlIntgErrCmd] | 113 | 1 | T130 | 2 | T131 | 8 | T132 | 5 | ||||
auto[TlIntgErrData] | 106 | 1 | T130 | 3 | T131 | 6 | T132 | 9 | ||||
auto[TlIntgErrBoth] | 111 | 1 | T130 | 5 | T131 | 6 | T132 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |