Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 3611126 1 T2 1 T4 1 T5 3
full_word 1049413 1 T5 5 T6 2 T28 2



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4660209 1 T2 1 T4 1 T5 8
auto[TlIntgErrCmd] 121 1 T130 3 T131 8 T132 9
auto[TlIntgErrData] 98 1 T130 2 T131 7 T132 4
auto[TlIntgErrBoth] 111 1 T130 5 T131 5 T132 7



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 728581 1 T5 2 T6 1 T28 3
auto[1] 3931958 1 T2 1 T4 1 T5 6



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 318956 1 T5 1 T6 1 T28 2
auto[TlIntgErrNone] partial auto[1] 3291871 1 T2 1 T4 1 T5 2
auto[TlIntgErrNone] full_word auto[0] 409471 1 T5 1 T28 1 T48 6
auto[TlIntgErrNone] full_word auto[1] 639911 1 T5 4 T6 2 T28 1
auto[TlIntgErrCmd] partial auto[0] 50 1 T130 1 T131 3 T132 2
auto[TlIntgErrCmd] partial auto[1] 59 1 T130 2 T131 5 T132 7
auto[TlIntgErrCmd] full_word auto[0] 4 1 T156 1 T157 1 T161 1
auto[TlIntgErrCmd] full_word auto[1] 8 1 T127 1 T156 1 T162 2
auto[TlIntgErrData] partial auto[0] 48 1 T131 4 T132 2 T128 4
auto[TlIntgErrData] partial auto[1] 43 1 T130 2 T131 3 T132 2
auto[TlIntgErrData] full_word auto[0] 4 1 T159 2 T163 1 T164 1
auto[TlIntgErrData] full_word auto[1] 3 1 T157 2 T165 1 - -
auto[TlIntgErrBoth] partial auto[0] 43 1 T130 2 T131 1 T132 4
auto[TlIntgErrBoth] partial auto[1] 56 1 T130 3 T131 4 T132 2
auto[TlIntgErrBoth] full_word auto[0] 5 1 T127 1 T128 1 T159 1
auto[TlIntgErrBoth] full_word auto[1] 7 1 T132 1 T159 1 T157 1

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