Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 162917591 871853 0 0
late_debug_enable_rd_A 162917591 111420 0 0
late_debug_enable_regwen_rd_A 162917591 100415 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162917591 871853 0 0
T8 110378 21798 0 0
T11 458495 0 0 0
T17 0 267584 0 0
T22 0 66831 0 0
T23 0 210630 0 0
T27 40011 0 0 0
T46 0 96207 0 0
T56 6557 0 0 0
T61 0 1803 0 0
T63 52725 0 0 0
T81 220075 0 0 0
T82 0 25229 0 0
T83 0 468 0 0
T84 0 199 0 0
T85 0 400 0 0
T86 2207 0 0 0
T87 6562 0 0 0
T88 1427 0 0 0
T89 121102 0 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162917591 111420 0 0
T8 110378 7493 0 0
T11 458495 0 0 0
T17 0 94031 0 0
T27 40011 0 0 0
T56 6557 0 0 0
T61 0 795 0 0
T63 52725 0 0 0
T81 220075 0 0 0
T83 0 116 0 0
T85 0 121 0 0
T86 2207 0 0 0
T87 6562 0 0 0
T88 1427 0 0 0
T89 121102 0 0 0
T95 0 53 0 0
T126 0 140 0 0
T127 0 48 0 0
T128 0 82 0 0
T129 0 26 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162917591 100415 0 0
T8 110378 6843 0 0
T11 458495 0 0 0
T17 0 83159 0 0
T27 40011 0 0 0
T56 6557 0 0 0
T61 0 582 0 0
T63 52725 0 0 0
T81 220075 0 0 0
T83 0 130 0 0
T85 0 91 0 0
T86 2207 0 0 0
T87 6562 0 0 0
T88 1427 0 0 0
T89 121102 0 0 0
T93 0 9 0 0
T95 0 11 0 0
T126 0 110 0 0
T127 0 57 0 0
T128 0 98 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%