Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T2 |
0 | 1 | Covered | T1,T7,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T7,T2 |
1 | 1 | Covered | T1,T7,T2 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
13771452 |
13770036 |
0 |
0 |
selKnown1 |
88072715 |
88071299 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
13771452 |
13770036 |
0 |
0 |
T1 |
18570 |
18568 |
0 |
0 |
T2 |
1208 |
1206 |
0 |
0 |
T3 |
1920 |
1917 |
0 |
0 |
T4 |
2037 |
2035 |
0 |
0 |
T5 |
17464 |
17460 |
0 |
0 |
T6 |
28342 |
28338 |
0 |
0 |
T7 |
325 |
323 |
0 |
0 |
T8 |
0 |
11 |
0 |
0 |
T13 |
138501 |
138497 |
0 |
0 |
T14 |
2 |
0 |
0 |
0 |
T24 |
0 |
7 |
0 |
0 |
T26 |
12 |
10 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T28 |
12 |
10 |
0 |
0 |
T32 |
11994 |
11990 |
0 |
0 |
T33 |
415 |
411 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T55 |
3 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
88072715 |
88071299 |
0 |
0 |
T1 |
52848 |
52846 |
0 |
0 |
T2 |
27449 |
27447 |
0 |
0 |
T3 |
7975 |
7973 |
0 |
0 |
T4 |
11164 |
11162 |
0 |
0 |
T5 |
338055 |
338051 |
0 |
0 |
T6 |
910334 |
910330 |
0 |
0 |
T7 |
11061 |
11059 |
0 |
0 |
T8 |
0 |
10 |
0 |
0 |
T13 |
180152 |
180149 |
0 |
0 |
T14 |
2 |
0 |
0 |
0 |
T24 |
0 |
6 |
0 |
0 |
T26 |
12 |
10 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T28 |
12 |
10 |
0 |
0 |
T32 |
28088 |
28084 |
0 |
0 |
T33 |
3582 |
3578 |
0 |
0 |
T50 |
2 |
0 |
0 |
0 |
T55 |
2 |
0 |
0 |
0 |
T56 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T2 |
0 | 1 | Covered | T1,T7,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T7,T2 |
1 | 1 | Covered | T1,T7,T2 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
4639166 |
4638922 |
0 |
0 |
selKnown1 |
78940828 |
78940584 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
4639166 |
4638922 |
0 |
0 |
T1 |
9285 |
9284 |
0 |
0 |
T2 |
604 |
603 |
0 |
0 |
T3 |
959 |
958 |
0 |
0 |
T4 |
1018 |
1017 |
0 |
0 |
T5 |
8726 |
8725 |
0 |
0 |
T6 |
14164 |
14163 |
0 |
0 |
T7 |
162 |
161 |
0 |
0 |
T13 |
69242 |
69241 |
0 |
0 |
T32 |
5993 |
5992 |
0 |
0 |
T33 |
206 |
205 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
78940828 |
78940584 |
0 |
0 |
T1 |
43563 |
43562 |
0 |
0 |
T2 |
26845 |
26844 |
0 |
0 |
T3 |
7016 |
7015 |
0 |
0 |
T4 |
10146 |
10145 |
0 |
0 |
T5 |
329319 |
329318 |
0 |
0 |
T6 |
896158 |
896157 |
0 |
0 |
T7 |
10899 |
10898 |
0 |
0 |
T13 |
110894 |
110894 |
0 |
0 |
T32 |
22091 |
22090 |
0 |
0 |
T33 |
3374 |
3373 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T2 |
0 | 1 | Covered | T1,T7,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T7,T2 |
1 | 1 | Covered | T1,T7,T2 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
756 |
512 |
0 |
0 |
T5 |
5 |
4 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T8 |
0 |
6 |
0 |
0 |
T13 |
8 |
7 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T24 |
0 |
3 |
0 |
0 |
T26 |
6 |
5 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T28 |
6 |
5 |
0 |
0 |
T32 |
3 |
2 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T55 |
1 |
0 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
702 |
458 |
0 |
0 |
T5 |
5 |
4 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T13 |
8 |
7 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T24 |
0 |
3 |
0 |
0 |
T26 |
6 |
5 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T28 |
6 |
5 |
0 |
0 |
T32 |
2 |
1 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T55 |
1 |
0 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T2 |
0 | 1 | Covered | T1,T7,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T7,T2 |
1 | 1 | Covered | T1,T7,T2 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9129533 |
9129069 |
0 |
0 |
selKnown1 |
9129305 |
9128841 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9129533 |
9129069 |
0 |
0 |
T1 |
9285 |
9284 |
0 |
0 |
T2 |
604 |
603 |
0 |
0 |
T3 |
959 |
958 |
0 |
0 |
T4 |
1019 |
1018 |
0 |
0 |
T5 |
8727 |
8726 |
0 |
0 |
T6 |
14165 |
14164 |
0 |
0 |
T7 |
163 |
162 |
0 |
0 |
T13 |
69243 |
69242 |
0 |
0 |
T32 |
5994 |
5993 |
0 |
0 |
T33 |
207 |
206 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9129305 |
9128841 |
0 |
0 |
T1 |
9285 |
9284 |
0 |
0 |
T2 |
604 |
603 |
0 |
0 |
T3 |
959 |
958 |
0 |
0 |
T4 |
1018 |
1017 |
0 |
0 |
T5 |
8726 |
8725 |
0 |
0 |
T6 |
14164 |
14163 |
0 |
0 |
T7 |
162 |
161 |
0 |
0 |
T13 |
69242 |
69241 |
0 |
0 |
T32 |
5993 |
5992 |
0 |
0 |
T33 |
206 |
205 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T2 |
0 | 1 | Covered | T1,T7,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T7,T2 |
1 | 1 | Covered | T1,T7,T2 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1997 |
1533 |
0 |
0 |
selKnown1 |
1880 |
1416 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1997 |
1533 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T13 |
8 |
7 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
T26 |
6 |
5 |
0 |
0 |
T28 |
6 |
5 |
0 |
0 |
T32 |
4 |
3 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T55 |
2 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1880 |
1416 |
0 |
0 |
T5 |
5 |
4 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T13 |
8 |
7 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T24 |
0 |
3 |
0 |
0 |
T26 |
6 |
5 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T28 |
6 |
5 |
0 |
0 |
T32 |
2 |
1 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T55 |
1 |
0 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |