Unified Coverage Report :: Module :: tlul_lc_gate

Module : tlul_lc_gate

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.94	100.00	88.89		100.00	95.83	50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_lc_gate_sba	68.13	86.27	72.22		57.14	75.00	50.00
tb.dut.u_tlul_lc_gate_rom	84.09	100.00	88.89		85.71	95.83	50.00

---

Module Instance : tb.dut.u_tlul_lc_gate_sba

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.13	86.27	72.22		57.14	75.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.08	94.49	75.00		57.14	81.25	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d	100.00	100.00
u_err_en_sync	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00
u_tlul_err_resp	95.00	100.00	80.00			100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_rom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.09	100.00	88.89		85.71	95.83	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.16	100.00	85.71		85.71	96.88	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d	100.00	100.00
u_err_en_sync	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00
u_tlul_err_resp	95.00	100.00	80.00			100.00	100.00

Line Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
TOTAL		51	51	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	28	100.00
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
			MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : tlul_lc_gate

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T2
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T7,T2
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T2
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T2
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T8,T17,T22
1	Covered	T5,T6,T28

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T8,T23
1	Covered	T1,T2,T4

---

FSM Coverage for Module : tlul_lc_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T1,T2,T4
StError	184	Covered	T1,T7,T2
StErrorOutstanding	203	Covered	T1,T2,T4
StFlush	184	Covered	T5,T6,T28
StOutstanding	174	Covered	T5,T6,T28

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T5,T6,T28
StError->StErrorOutstanding	203	Covered	T1,T2,T4
StErrorOutstanding->StActive	211	Covered	T1,T2,T4
StFlush->StActive	196	Covered	T6,T28,T8
StFlush->StError	194	Covered	T5,T6,T24
StOutstanding->StError	184	Covered	T5,T6,T24
StOutstanding->StFlush	184	Covered	T5,T6,T28

---

Branch Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	14	13	92.86
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T2
0	Covered	T1,T7,T2

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T2
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T7,T2

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T5,T6,T28
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T4
StActive	-	1	-	-	-	-	-	Covered	T1,T2,T4
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T4
StOutstanding	-	-	1	-	-	-	-	Covered	T5,T6,T28
StOutstanding	-	-	0	-	-	-	-	Covered	T8,T17,T22
StFlush	-	-	-	1	-	-	-	Covered	T5,T6,T24
StFlush	-	-	-	0	1	-	-	Covered	T6,T28,T8
StFlush	-	-	-	0	0	-	-	Covered	T5,T6,T28
StError	-	-	-	-	-	1	-	Covered	T1,T2,T4
StError	-	-	-	-	-	0	-	Covered	T1,T7,T2
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T4
StErrorOutstanding	-	-	-	-	-	-	0	Covered	T8,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T2
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T7,T2

---

Assert Coverage for Module : tlul_lc_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	157881656	0	0	0
u_state_regs_A	157881656	157776036	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157881656	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157881656	157776036	0	0
T1	87126	86976	0	0
T2	53690	53556	0	0
T3	14032	13868	0	0
T4	20292	20192	0	0
T5	658638	657948	0	0
T6	1792316	1791630	0	0
T7	21798	21696	0	0
T13	221788	221682	0	0
T32	44182	43950	0	0
T33	6748	6628	0	0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba

	Line No.	Total	Covered	Percent
TOTAL		51	44	86.27
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	21	75.00
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	0	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			==> MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_sba

	Total	Covered	Percent
Conditions	18	13	72.22
Logical	18	13	72.22
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T2
1	0	Covered	T14,T26,T57
1	1	Covered	T1,T13,T14

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T7,T2
1	1	Covered	T1,T13,T14

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T2
1	0	Not Covered
1	1	Covered	T1,T13,T14

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T2
1	0	Not Covered
1	1	Covered	T1,T13,T14

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T13,T14

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T6,T24

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.u_tlul_lc_gate_sba

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	7	4	57.14
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T1,T2,T4
StError	184	Covered	T1,T7,T2
StErrorOutstanding	203	Covered	T1,T2,T4
StFlush	184	Not Covered
StOutstanding	174	Covered	T5,T6,T24

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T5,T6,T24
StError->StErrorOutstanding	203	Covered	T1,T2,T4
StErrorOutstanding->StActive	211	Covered	T1,T2,T4
StFlush->StActive	196	Not Covered
StFlush->StError	194	Not Covered
StOutstanding->StError	184	Covered	T5,T6,T24
StOutstanding->StFlush	184	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_sba

	Line No.	Total	Covered	Percent
Branches		24	18	75.00
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	14	8	57.14
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T2
0	Covered	T1,T7,T2

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T2
0	1	-	Covered	T1,T13,T14
0	0	1	Covered	T1,T13,T14
0	0	0	Covered	T1,T7,T2

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T5,T6,T24
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T4
StActive	-	1	-	-	-	-	-	Covered	T1,T13,T14
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T4
StOutstanding	-	-	1	-	-	-	-	Covered	T5,T6,T24
StOutstanding	-	-	0	-	-	-	-	Not Covered
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Not Covered
StFlush	-	-	-	0	0	-	-	Not Covered
StError	-	-	-	-	-	1	-	Covered	T1,T2,T4
StError	-	-	-	-	-	0	-	Covered	T1,T7,T2
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T4
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T2
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T7,T2

---

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	78940828	0	0	0
u_state_regs_A	78940828	78888018	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78940828	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78940828	78888018	0	0
T1	43563	43488	0	0
T2	26845	26778	0	0
T3	7016	6934	0	0
T4	10146	10096	0	0
T5	329319	328974	0	0
T6	896158	895815	0	0
T7	10899	10848	0	0
T13	110894	110841	0	0
T32	22091	21975	0	0
T33	3374	3314	0	0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom

	Line No.	Total	Covered	Percent
TOTAL		51	51	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	28	100.00
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
			MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_rom

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T2
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T7,T2
1	1	Covered	T2,T4,T5

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T2
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T2
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T5

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T8,T17,T22
1	Covered	T5,T6,T28

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T8,T23
1	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.u_tlul_lc_gate_rom

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	6	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T1,T2,T4
StError	184	Covered	T1,T7,T2
StErrorOutstanding	203	Covered	T1,T2,T4
StFlush	184	Covered	T5,T6,T28
StOutstanding	174	Covered	T5,T6,T28

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T5,T6,T28
StError->StErrorOutstanding	203	Covered	T1,T2,T4
StErrorOutstanding->StActive	211	Covered	T1,T2,T4
StFlush->StActive	196	Covered	T6,T28,T8
StFlush->StError	194	Covered	T5,T6,T24
StOutstanding->StError	184	Not Covered
StOutstanding->StFlush	184	Covered	T5,T6,T28

---

Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_rom

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	14	13	92.86
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T2
0	Covered	T1,T7,T2

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T2
0	1	-	Covered	T2,T4,T5
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T7,T2

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T5,T6,T28
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T4
StActive	-	1	-	-	-	-	-	Covered	T2,T4,T5
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T4
StOutstanding	-	-	1	-	-	-	-	Covered	T5,T6,T28
StOutstanding	-	-	0	-	-	-	-	Covered	T8,T17,T22
StFlush	-	-	-	1	-	-	-	Covered	T5,T6,T24
StFlush	-	-	-	0	1	-	-	Covered	T6,T28,T8
StFlush	-	-	-	0	0	-	-	Covered	T5,T6,T28
StError	-	-	-	-	-	1	-	Covered	T1,T2,T4
StError	-	-	-	-	-	0	-	Covered	T1,T7,T2
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T4
StErrorOutstanding	-	-	-	-	-	-	0	Covered	T8,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T2
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T7,T2

---

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	78940828	0	0	0
u_state_regs_A	78940828	78888018	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78940828	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78940828	78888018	0	0
T1	43563	43488	0	0
T2	26845	26778	0	0
T3	7016	6934	0	0
T4	10146	10096	0	0
T5	329319	328974	0	0
T6	896158	895815	0	0
T7	10899	10848	0	0
T13	110894	110841	0	0
T32	22091	21975	0	0
T33	3374	3314	0	0