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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.53 96.18 85.48 89.91 72.50 88.33 98.21 54.13


Total test records in report: 466
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T306 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1107040174 Aug 06 04:36:27 PM PDT 24 Aug 06 04:36:29 PM PDT 24 1225828461 ps
T51 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1117672696 Aug 06 04:36:35 PM PDT 24 Aug 06 04:36:36 PM PDT 24 111271945 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3209767530 Aug 06 04:36:25 PM PDT 24 Aug 06 04:37:04 PM PDT 24 13077824586 ps
T78 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1664111089 Aug 06 04:36:33 PM PDT 24 Aug 06 04:36:36 PM PDT 24 547367532 ps
T79 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1428643747 Aug 06 04:36:37 PM PDT 24 Aug 06 04:36:44 PM PDT 24 389374367 ps
T80 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.279944150 Aug 06 04:36:45 PM PDT 24 Aug 06 04:36:53 PM PDT 24 449246865 ps
T81 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3078718733 Aug 06 04:36:54 PM PDT 24 Aug 06 04:36:56 PM PDT 24 113154702 ps
T89 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2887531553 Aug 06 04:36:08 PM PDT 24 Aug 06 04:36:13 PM PDT 24 3107771070 ps
T77 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3562722885 Aug 06 04:36:55 PM PDT 24 Aug 06 04:37:23 PM PDT 24 4646791656 ps
T82 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1145891983 Aug 06 04:36:50 PM PDT 24 Aug 06 04:36:59 PM PDT 24 887852938 ps
T88 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2333246132 Aug 06 04:36:51 PM PDT 24 Aug 06 04:37:03 PM PDT 24 1007822836 ps
T48 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.114034517 Aug 06 04:36:04 PM PDT 24 Aug 06 04:39:57 PM PDT 24 48830178764 ps
T83 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1212632750 Aug 06 04:36:54 PM PDT 24 Aug 06 04:37:02 PM PDT 24 636793592 ps
T308 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.942830736 Aug 06 04:36:19 PM PDT 24 Aug 06 04:36:21 PM PDT 24 61968099 ps
T309 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.913620 Aug 06 04:36:05 PM PDT 24 Aug 06 04:36:05 PM PDT 24 126116367 ps
T52 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1045601095 Aug 06 04:36:36 PM PDT 24 Aug 06 04:36:37 PM PDT 24 677201689 ps
T310 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4038013641 Aug 06 04:37:05 PM PDT 24 Aug 06 04:37:07 PM PDT 24 101144992 ps
T112 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.154762785 Aug 06 04:36:52 PM PDT 24 Aug 06 04:36:56 PM PDT 24 333791247 ps
T113 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2364507443 Aug 06 04:36:55 PM PDT 24 Aug 06 04:36:59 PM PDT 24 346499896 ps
T154 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3097100070 Aug 06 04:36:21 PM PDT 24 Aug 06 04:36:37 PM PDT 24 1829023597 ps
T49 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4032119050 Aug 06 04:36:47 PM PDT 24 Aug 06 04:37:54 PM PDT 24 51739272189 ps
T155 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1699816678 Aug 06 04:36:36 PM PDT 24 Aug 06 04:36:47 PM PDT 24 3016152983 ps
T311 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.966415249 Aug 06 04:36:49 PM PDT 24 Aug 06 04:36:55 PM PDT 24 519920154 ps
T312 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.631320197 Aug 06 04:36:56 PM PDT 24 Aug 06 04:37:01 PM PDT 24 351331888 ps
T84 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3011096343 Aug 06 04:36:24 PM PDT 24 Aug 06 04:36:31 PM PDT 24 186681803 ps
T313 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3730482201 Aug 06 04:36:50 PM PDT 24 Aug 06 04:36:53 PM PDT 24 568303113 ps
T314 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.876077257 Aug 06 04:36:55 PM PDT 24 Aug 06 04:37:00 PM PDT 24 5338044734 ps
T85 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2799295690 Aug 06 04:36:36 PM PDT 24 Aug 06 04:36:39 PM PDT 24 245841838 ps
T86 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.256534448 Aug 06 04:36:39 PM PDT 24 Aug 06 04:36:42 PM PDT 24 127736989 ps
T87 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3914449218 Aug 06 04:36:31 PM PDT 24 Aug 06 04:36:34 PM PDT 24 386131029 ps
T94 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2662638895 Aug 06 04:36:33 PM PDT 24 Aug 06 04:36:36 PM PDT 24 249282049 ps
T114 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3331275467 Aug 06 04:36:20 PM PDT 24 Aug 06 04:36:24 PM PDT 24 615389851 ps
T115 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3437826167 Aug 06 04:36:21 PM PDT 24 Aug 06 04:36:26 PM PDT 24 257479418 ps
T95 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4287424607 Aug 06 04:36:54 PM PDT 24 Aug 06 04:37:02 PM PDT 24 539346882 ps
T96 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3542761110 Aug 06 04:37:01 PM PDT 24 Aug 06 04:37:27 PM PDT 24 837348791 ps
T315 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1813676495 Aug 06 04:36:54 PM PDT 24 Aug 06 04:36:56 PM PDT 24 178912513 ps
T316 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4239852321 Aug 06 04:36:42 PM PDT 24 Aug 06 04:36:44 PM PDT 24 104291676 ps
T97 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2557599221 Aug 06 04:37:01 PM PDT 24 Aug 06 04:37:02 PM PDT 24 172351633 ps
T53 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1539269323 Aug 06 04:36:09 PM PDT 24 Aug 06 04:36:15 PM PDT 24 6906002841 ps
T317 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1779647333 Aug 06 04:36:53 PM PDT 24 Aug 06 04:36:54 PM PDT 24 110394856 ps
T107 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.253339433 Aug 06 04:37:00 PM PDT 24 Aug 06 04:37:07 PM PDT 24 170068313 ps
T318 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3458615410 Aug 06 04:36:57 PM PDT 24 Aug 06 04:37:01 PM PDT 24 166357099 ps
T319 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2780591419 Aug 06 04:36:37 PM PDT 24 Aug 06 04:36:42 PM PDT 24 839946667 ps
T102 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1420229175 Aug 06 04:36:45 PM PDT 24 Aug 06 04:36:47 PM PDT 24 140761983 ps
T320 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1686169685 Aug 06 04:36:38 PM PDT 24 Aug 06 04:36:42 PM PDT 24 492624943 ps
T321 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2105923417 Aug 06 04:36:08 PM PDT 24 Aug 06 04:36:33 PM PDT 24 2283314641 ps
T103 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2362984640 Aug 06 04:36:57 PM PDT 24 Aug 06 04:37:00 PM PDT 24 169806670 ps
T322 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1834777154 Aug 06 04:37:01 PM PDT 24 Aug 06 04:37:04 PM PDT 24 322536124 ps
T323 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2275332794 Aug 06 04:36:08 PM PDT 24 Aug 06 04:36:11 PM PDT 24 5730549179 ps
T161 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3377836889 Aug 06 04:36:38 PM PDT 24 Aug 06 04:36:49 PM PDT 24 32665283276 ps
T324 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4078569670 Aug 06 04:36:30 PM PDT 24 Aug 06 04:37:52 PM PDT 24 54791005687 ps
T325 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3939770658 Aug 06 04:36:47 PM PDT 24 Aug 06 04:36:49 PM PDT 24 117979862 ps
T326 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3232213565 Aug 06 04:37:05 PM PDT 24 Aug 06 04:37:06 PM PDT 24 259157257 ps
T327 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3487594923 Aug 06 04:36:45 PM PDT 24 Aug 06 04:37:06 PM PDT 24 17493334286 ps
T328 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1648847679 Aug 06 04:36:31 PM PDT 24 Aug 06 04:36:35 PM PDT 24 3601377107 ps
T329 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1441420117 Aug 06 04:36:24 PM PDT 24 Aug 06 04:36:28 PM PDT 24 379805814 ps
T90 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.123519564 Aug 06 04:37:00 PM PDT 24 Aug 06 04:37:10 PM PDT 24 3291819657 ps
T330 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.441779242 Aug 06 04:36:17 PM PDT 24 Aug 06 04:36:25 PM PDT 24 19411702741 ps
T108 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1911138979 Aug 06 04:37:03 PM PDT 24 Aug 06 04:37:09 PM PDT 24 183768087 ps
T104 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.589379054 Aug 06 04:36:22 PM PDT 24 Aug 06 04:36:25 PM PDT 24 433516905 ps
T331 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2219322995 Aug 06 04:36:51 PM PDT 24 Aug 06 04:36:53 PM PDT 24 211223495 ps
T332 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.310753801 Aug 06 04:36:55 PM PDT 24 Aug 06 04:36:56 PM PDT 24 545122809 ps
T333 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1157962159 Aug 06 04:36:37 PM PDT 24 Aug 06 04:36:42 PM PDT 24 307664600 ps
T151 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.89608645 Aug 06 04:36:21 PM PDT 24 Aug 06 04:36:44 PM PDT 24 5067619931 ps
T334 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3928194801 Aug 06 04:36:23 PM PDT 24 Aug 06 04:36:24 PM PDT 24 1110824523 ps
T335 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2825119495 Aug 06 04:36:46 PM PDT 24 Aug 06 04:36:52 PM PDT 24 389054851 ps
T162 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.320347076 Aug 06 04:36:34 PM PDT 24 Aug 06 04:38:54 PM PDT 24 47901063537 ps
T336 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2606549210 Aug 06 04:36:27 PM PDT 24 Aug 06 04:36:32 PM PDT 24 347365260 ps
T105 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2781135187 Aug 06 04:36:19 PM PDT 24 Aug 06 04:36:21 PM PDT 24 643760839 ps
T337 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1824296343 Aug 06 04:36:09 PM PDT 24 Aug 06 04:36:27 PM PDT 24 18971475975 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3006805839 Aug 06 04:36:09 PM PDT 24 Aug 06 04:36:13 PM PDT 24 551833626 ps
T339 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2421046546 Aug 06 04:36:22 PM PDT 24 Aug 06 04:36:45 PM PDT 24 19757725751 ps
T98 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1023054215 Aug 06 04:36:51 PM PDT 24 Aug 06 04:36:54 PM PDT 24 291470427 ps
T340 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4276311376 Aug 06 04:36:24 PM PDT 24 Aug 06 04:36:25 PM PDT 24 41192461 ps
T341 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1373122113 Aug 06 04:36:19 PM PDT 24 Aug 06 04:37:02 PM PDT 24 26258424232 ps
T342 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3649025236 Aug 06 04:36:50 PM PDT 24 Aug 06 04:36:51 PM PDT 24 32949092 ps
T343 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3733649935 Aug 06 04:36:36 PM PDT 24 Aug 06 04:36:38 PM PDT 24 3733160152 ps
T344 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4158447739 Aug 06 04:36:53 PM PDT 24 Aug 06 04:36:58 PM PDT 24 506467661 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.240833841 Aug 06 04:36:40 PM PDT 24 Aug 06 04:36:43 PM PDT 24 1165028213 ps
T346 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3717133789 Aug 06 04:36:37 PM PDT 24 Aug 06 04:37:50 PM PDT 24 90659213048 ps
T347 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2523294313 Aug 06 04:36:43 PM PDT 24 Aug 06 04:37:25 PM PDT 24 63031557440 ps
T348 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2980772518 Aug 06 04:36:25 PM PDT 24 Aug 06 04:36:30 PM PDT 24 1560352518 ps
T349 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.101044259 Aug 06 04:36:51 PM PDT 24 Aug 06 04:36:53 PM PDT 24 1421081466 ps
T350 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2271427201 Aug 06 04:36:49 PM PDT 24 Aug 06 04:36:52 PM PDT 24 241340266 ps
T91 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1973041925 Aug 06 04:36:37 PM PDT 24 Aug 06 04:36:49 PM PDT 24 3430118349 ps
T351 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.815900917 Aug 06 04:36:57 PM PDT 24 Aug 06 04:36:58 PM PDT 24 256299632 ps
T352 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1024186450 Aug 06 04:36:38 PM PDT 24 Aug 06 04:36:39 PM PDT 24 60957984 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3200788799 Aug 06 04:36:09 PM PDT 24 Aug 06 04:36:10 PM PDT 24 484898526 ps
T152 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2192251014 Aug 06 04:36:54 PM PDT 24 Aug 06 04:37:14 PM PDT 24 9740211085 ps
T354 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.47930204 Aug 06 04:36:52 PM PDT 24 Aug 06 04:36:57 PM PDT 24 98987504 ps
T355 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1234385566 Aug 06 04:36:54 PM PDT 24 Aug 06 04:37:03 PM PDT 24 10491040272 ps
T356 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.14790605 Aug 06 04:36:39 PM PDT 24 Aug 06 04:36:48 PM PDT 24 12521067674 ps
T357 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2959962839 Aug 06 04:36:44 PM PDT 24 Aug 06 04:36:45 PM PDT 24 47780691 ps
T358 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.363223062 Aug 06 04:36:36 PM PDT 24 Aug 06 04:36:38 PM PDT 24 2063496168 ps
T359 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1997281325 Aug 06 04:36:52 PM PDT 24 Aug 06 04:36:53 PM PDT 24 186698379 ps
T159 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1610506795 Aug 06 04:36:09 PM PDT 24 Aug 06 04:36:20 PM PDT 24 1488213852 ps
T109 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1132559432 Aug 06 04:36:57 PM PDT 24 Aug 06 04:37:01 PM PDT 24 1151911815 ps
T360 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.471698883 Aug 06 04:36:25 PM PDT 24 Aug 06 04:37:35 PM PDT 24 20492367575 ps
T361 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2614604683 Aug 06 04:36:05 PM PDT 24 Aug 06 04:36:06 PM PDT 24 213625653 ps
T362 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.4175573169 Aug 06 04:36:25 PM PDT 24 Aug 06 04:36:45 PM PDT 24 22665407665 ps
T363 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3647492338 Aug 06 04:36:51 PM PDT 24 Aug 06 04:36:58 PM PDT 24 8522212214 ps
T364 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3401046083 Aug 06 04:36:16 PM PDT 24 Aug 06 04:36:36 PM PDT 24 14740293169 ps
T92 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.618624862 Aug 06 04:36:23 PM PDT 24 Aug 06 04:36:36 PM PDT 24 8245368625 ps
T110 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2887783904 Aug 06 04:36:33 PM PDT 24 Aug 06 04:36:40 PM PDT 24 197470144 ps
T106 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1078396672 Aug 06 04:36:15 PM PDT 24 Aug 06 04:36:18 PM PDT 24 211763908 ps
T365 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2870918878 Aug 06 04:36:19 PM PDT 24 Aug 06 04:37:15 PM PDT 24 37680316622 ps
T366 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3183144681 Aug 06 04:36:37 PM PDT 24 Aug 06 04:36:41 PM PDT 24 268444357 ps
T367 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2939944718 Aug 06 04:36:05 PM PDT 24 Aug 06 04:36:09 PM PDT 24 1145701347 ps
T368 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2910704809 Aug 06 04:36:19 PM PDT 24 Aug 06 04:36:20 PM PDT 24 894079337 ps
T369 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1745196293 Aug 06 04:36:25 PM PDT 24 Aug 06 04:36:26 PM PDT 24 128280198 ps
T153 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2575872105 Aug 06 04:36:34 PM PDT 24 Aug 06 04:36:59 PM PDT 24 10586242668 ps
T370 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.377077947 Aug 06 04:36:40 PM PDT 24 Aug 06 04:36:45 PM PDT 24 268784572 ps
T371 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.98327831 Aug 06 04:36:24 PM PDT 24 Aug 06 04:36:26 PM PDT 24 111750969 ps
T372 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1342730646 Aug 06 04:36:35 PM PDT 24 Aug 06 04:38:19 PM PDT 24 13806471173 ps
T99 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.861167799 Aug 06 04:36:43 PM PDT 24 Aug 06 04:36:48 PM PDT 24 794798863 ps
T373 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2610129 Aug 06 04:36:36 PM PDT 24 Aug 06 04:36:51 PM PDT 24 5455305586 ps
T374 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3224581891 Aug 06 04:36:37 PM PDT 24 Aug 06 04:36:40 PM PDT 24 295207908 ps
T375 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1349984217 Aug 06 04:36:27 PM PDT 24 Aug 06 04:36:28 PM PDT 24 541883068 ps
T376 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1619919826 Aug 06 04:36:42 PM PDT 24 Aug 06 04:36:44 PM PDT 24 973351619 ps
T377 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2317718944 Aug 06 04:36:31 PM PDT 24 Aug 06 04:37:49 PM PDT 24 30244397343 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1825474237 Aug 06 04:36:17 PM PDT 24 Aug 06 04:37:10 PM PDT 24 60767953934 ps
T379 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.905563618 Aug 06 04:36:51 PM PDT 24 Aug 06 04:36:55 PM PDT 24 1010352050 ps
T380 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3212471239 Aug 06 04:36:57 PM PDT 24 Aug 06 04:37:15 PM PDT 24 10390332634 ps
T381 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3991688345 Aug 06 04:36:56 PM PDT 24 Aug 06 04:36:59 PM PDT 24 78579011 ps
T382 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2615369036 Aug 06 04:36:53 PM PDT 24 Aug 06 04:37:01 PM PDT 24 1343345013 ps
T383 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1749274924 Aug 06 04:36:31 PM PDT 24 Aug 06 04:36:36 PM PDT 24 2632668699 ps
T160 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.282214122 Aug 06 04:36:53 PM PDT 24 Aug 06 04:37:04 PM PDT 24 1333329162 ps
T384 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3093233642 Aug 06 04:36:49 PM PDT 24 Aug 06 04:37:47 PM PDT 24 20359089055 ps
T385 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3036232013 Aug 06 04:36:40 PM PDT 24 Aug 06 04:36:41 PM PDT 24 231213827 ps
T386 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1354197236 Aug 06 04:36:50 PM PDT 24 Aug 06 04:36:56 PM PDT 24 1512278673 ps
T387 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3915744356 Aug 06 04:36:57 PM PDT 24 Aug 06 04:37:02 PM PDT 24 276360850 ps
T388 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1886066789 Aug 06 04:36:59 PM PDT 24 Aug 06 04:37:01 PM PDT 24 329357273 ps
T389 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3886320564 Aug 06 04:36:54 PM PDT 24 Aug 06 04:37:05 PM PDT 24 2492472826 ps
T390 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.528537010 Aug 06 04:36:54 PM PDT 24 Aug 06 04:36:58 PM PDT 24 2011358772 ps
T391 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1355623947 Aug 06 04:36:58 PM PDT 24 Aug 06 04:37:01 PM PDT 24 266763282 ps
T392 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3473202828 Aug 06 04:36:40 PM PDT 24 Aug 06 04:36:50 PM PDT 24 2568617730 ps
T393 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1268661391 Aug 06 04:36:39 PM PDT 24 Aug 06 04:36:40 PM PDT 24 201805086 ps
T100 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2032713360 Aug 06 04:36:18 PM PDT 24 Aug 06 04:37:23 PM PDT 24 1541710150 ps
T101 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2378311689 Aug 06 04:36:52 PM PDT 24 Aug 06 04:36:55 PM PDT 24 298071710 ps
T394 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1852976886 Aug 06 04:37:01 PM PDT 24 Aug 06 04:37:03 PM PDT 24 403048464 ps
T395 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1212962064 Aug 06 04:36:17 PM PDT 24 Aug 06 04:36:22 PM PDT 24 5470721652 ps
T396 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2143379464 Aug 06 04:36:44 PM PDT 24 Aug 06 04:38:19 PM PDT 24 109007633207 ps
T397 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3426821295 Aug 06 04:36:40 PM PDT 24 Aug 06 04:36:41 PM PDT 24 319804063 ps
T93 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.971555003 Aug 06 04:36:27 PM PDT 24 Aug 06 04:36:32 PM PDT 24 3216657184 ps
T398 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.632415251 Aug 06 04:36:38 PM PDT 24 Aug 06 04:36:39 PM PDT 24 416929191 ps
T399 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1286487796 Aug 06 04:36:16 PM PDT 24 Aug 06 04:36:20 PM PDT 24 931167681 ps
T400 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3323318393 Aug 06 04:36:54 PM PDT 24 Aug 06 04:36:56 PM PDT 24 397108534 ps
T401 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2021892949 Aug 06 04:36:40 PM PDT 24 Aug 06 04:36:48 PM PDT 24 2292967115 ps
T402 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2310648054 Aug 06 04:36:35 PM PDT 24 Aug 06 04:36:41 PM PDT 24 513952455 ps
T403 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2259112153 Aug 06 04:36:25 PM PDT 24 Aug 06 04:36:26 PM PDT 24 358226024 ps
T404 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.902041229 Aug 06 04:36:54 PM PDT 24 Aug 06 04:36:59 PM PDT 24 2554721248 ps
T405 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1528925733 Aug 06 04:36:22 PM PDT 24 Aug 06 04:36:23 PM PDT 24 275393371 ps
T406 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3198956507 Aug 06 04:36:52 PM PDT 24 Aug 06 04:36:53 PM PDT 24 288333006 ps
T407 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.769726264 Aug 06 04:36:31 PM PDT 24 Aug 06 04:36:32 PM PDT 24 46173760 ps
T408 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1173954580 Aug 06 04:36:36 PM PDT 24 Aug 06 04:36:41 PM PDT 24 2942518836 ps
T409 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2308232729 Aug 06 04:36:40 PM PDT 24 Aug 06 04:36:48 PM PDT 24 11833131659 ps
T410 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1638265186 Aug 06 04:36:27 PM PDT 24 Aug 06 04:36:30 PM PDT 24 1185380297 ps
T411 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.954479648 Aug 06 04:36:52 PM PDT 24 Aug 06 04:36:54 PM PDT 24 787550290 ps
T412 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3836874525 Aug 06 04:36:47 PM PDT 24 Aug 06 04:36:49 PM PDT 24 196262863 ps
T413 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.101260854 Aug 06 04:37:00 PM PDT 24 Aug 06 04:37:05 PM PDT 24 408842389 ps
T156 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1637786514 Aug 06 04:36:56 PM PDT 24 Aug 06 04:37:12 PM PDT 24 3357635308 ps
T414 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2186961515 Aug 06 04:36:48 PM PDT 24 Aug 06 04:36:48 PM PDT 24 68626108 ps
T415 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2639443946 Aug 06 04:36:51 PM PDT 24 Aug 06 04:38:10 PM PDT 24 28025750727 ps
T416 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3878307335 Aug 06 04:36:35 PM PDT 24 Aug 06 04:36:51 PM PDT 24 13983835211 ps
T417 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.955553515 Aug 06 04:36:50 PM PDT 24 Aug 06 04:36:52 PM PDT 24 358816869 ps
T418 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3365192194 Aug 06 04:36:33 PM PDT 24 Aug 06 04:37:09 PM PDT 24 2133340470 ps
T419 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.363986034 Aug 06 04:36:38 PM PDT 24 Aug 06 04:36:41 PM PDT 24 1505680001 ps
T420 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3951656797 Aug 06 04:36:40 PM PDT 24 Aug 06 04:37:07 PM PDT 24 16650404996 ps
T421 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.574530566 Aug 06 04:36:51 PM PDT 24 Aug 06 04:36:56 PM PDT 24 3389616109 ps
T422 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2888197211 Aug 06 04:36:58 PM PDT 24 Aug 06 04:37:00 PM PDT 24 187771087 ps
T423 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.251747153 Aug 06 04:36:32 PM PDT 24 Aug 06 04:36:36 PM PDT 24 413731597 ps
T424 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1208488068 Aug 06 04:36:57 PM PDT 24 Aug 06 04:37:00 PM PDT 24 363426222 ps
T425 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1192882224 Aug 06 04:36:53 PM PDT 24 Aug 06 04:37:14 PM PDT 24 3004343412 ps
T157 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2403309321 Aug 06 04:36:54 PM PDT 24 Aug 06 04:37:04 PM PDT 24 1564990777 ps
T426 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4284160620 Aug 06 04:36:21 PM PDT 24 Aug 06 04:37:14 PM PDT 24 57525862820 ps
T427 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1500427737 Aug 06 04:36:24 PM PDT 24 Aug 06 04:36:25 PM PDT 24 123801768 ps
T428 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.616496450 Aug 06 04:36:57 PM PDT 24 Aug 06 04:36:59 PM PDT 24 96921196 ps
T429 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2504100284 Aug 06 04:36:57 PM PDT 24 Aug 06 04:37:00 PM PDT 24 2906108082 ps
T430 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.341773203 Aug 06 04:36:38 PM PDT 24 Aug 06 04:36:41 PM PDT 24 479946443 ps
T431 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.210570065 Aug 06 04:36:21 PM PDT 24 Aug 06 04:36:23 PM PDT 24 118605623 ps
T432 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1378153310 Aug 06 04:36:08 PM PDT 24 Aug 06 04:36:08 PM PDT 24 29681665 ps
T433 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3512622133 Aug 06 04:36:43 PM PDT 24 Aug 06 04:36:53 PM PDT 24 8017327422 ps
T434 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2797647032 Aug 06 04:36:56 PM PDT 24 Aug 06 04:37:00 PM PDT 24 4923417093 ps
T435 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.104018596 Aug 06 04:36:59 PM PDT 24 Aug 06 04:37:03 PM PDT 24 231678208 ps
T436 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.822873775 Aug 06 04:36:43 PM PDT 24 Aug 06 04:36:48 PM PDT 24 2632197567 ps
T437 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.60445756 Aug 06 04:36:16 PM PDT 24 Aug 06 04:36:18 PM PDT 24 512803584 ps
T438 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2149340333 Aug 06 04:36:38 PM PDT 24 Aug 06 04:37:53 PM PDT 24 7104320114 ps
T439 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.789603312 Aug 06 04:36:39 PM PDT 24 Aug 06 04:36:41 PM PDT 24 71364767 ps
T440 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1768467573 Aug 06 04:37:01 PM PDT 24 Aug 06 04:37:45 PM PDT 24 15606606525 ps
T441 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.192249012 Aug 06 04:36:49 PM PDT 24 Aug 06 04:36:52 PM PDT 24 710306249 ps
T442 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1491405857 Aug 06 04:36:39 PM PDT 24 Aug 06 04:36:43 PM PDT 24 512953228 ps
T443 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2932357327 Aug 06 04:36:20 PM PDT 24 Aug 06 04:36:21 PM PDT 24 103471865 ps
T444 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.265907725 Aug 06 04:36:49 PM PDT 24 Aug 06 04:37:07 PM PDT 24 1360178824 ps
T445 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2344003323 Aug 06 04:36:21 PM PDT 24 Aug 06 04:36:22 PM PDT 24 54554066 ps
T446 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.924413426 Aug 06 04:37:02 PM PDT 24 Aug 06 04:37:03 PM PDT 24 195287721 ps
T447 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.470074697 Aug 06 04:36:54 PM PDT 24 Aug 06 04:37:56 PM PDT 24 22641167501 ps
T448 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3066357985 Aug 06 04:36:51 PM PDT 24 Aug 06 04:36:52 PM PDT 24 450042424 ps
T449 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1934200601 Aug 06 04:36:39 PM PDT 24 Aug 06 04:36:40 PM PDT 24 928122397 ps
T450 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.703450581 Aug 06 04:36:50 PM PDT 24 Aug 06 04:36:58 PM PDT 24 893411750 ps
T451 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3443770163 Aug 06 04:36:19 PM PDT 24 Aug 06 04:36:24 PM PDT 24 289358091 ps
T452 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3165668150 Aug 06 04:36:51 PM PDT 24 Aug 06 04:36:58 PM PDT 24 28258908006 ps
T453 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3909483347 Aug 06 04:36:34 PM PDT 24 Aug 06 04:36:44 PM PDT 24 6769687943 ps
T454 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1095953609 Aug 06 04:36:09 PM PDT 24 Aug 06 04:36:13 PM PDT 24 1918446182 ps
T158 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1384501521 Aug 06 04:36:58 PM PDT 24 Aug 06 04:37:12 PM PDT 24 2637148761 ps
T455 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3261088151 Aug 06 04:36:24 PM PDT 24 Aug 06 04:36:44 PM PDT 24 4809141539 ps
T456 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1743431516 Aug 06 04:36:33 PM PDT 24 Aug 06 04:36:34 PM PDT 24 75497529 ps
T457 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1313959194 Aug 06 04:36:56 PM PDT 24 Aug 06 04:36:57 PM PDT 24 802162509 ps
T458 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1883712980 Aug 06 04:36:52 PM PDT 24 Aug 06 04:36:57 PM PDT 24 4498738830 ps
T459 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4282983563 Aug 06 04:36:32 PM PDT 24 Aug 06 04:36:39 PM PDT 24 4274577091 ps
T460 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4191349806 Aug 06 04:36:35 PM PDT 24 Aug 06 04:36:44 PM PDT 24 1693614979 ps
T461 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2835690919 Aug 06 04:36:37 PM PDT 24 Aug 06 04:36:45 PM PDT 24 5049319349 ps
T462 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.388323656 Aug 06 04:36:56 PM PDT 24 Aug 06 04:37:00 PM PDT 24 269724777 ps
T463 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2652105044 Aug 06 04:36:23 PM PDT 24 Aug 06 04:36:28 PM PDT 24 182340397 ps
T464 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.659037377 Aug 06 04:36:52 PM PDT 24 Aug 06 04:36:55 PM PDT 24 514417709 ps
T465 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1787960546 Aug 06 04:36:03 PM PDT 24 Aug 06 04:36:38 PM PDT 24 5684256073 ps
T466 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2991851100 Aug 06 04:36:51 PM PDT 24 Aug 06 04:36:53 PM PDT 24 1521948427 ps

Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.2866463719
Short name T5
Test name
Test status
Simulation time 133109648639 ps
CPU time 496.22 seconds
Started Aug 06 04:43:14 PM PDT 24
Finished Aug 06 04:51:30 PM PDT 24
Peak memory 230252 kb
Host smart-b5924980-a44d-45ae-a592-5ae85ae66f03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866463719 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.2866463719
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2555865997
Short name T2
Test name
Test status
Simulation time 56333019015 ps
CPU time 91.07 seconds
Started Aug 06 04:43:31 PM PDT 24
Finished Aug 06 04:45:02 PM PDT 24
Peak memory 213796 kb
Host smart-43a2588f-f542-4be2-9a49-2d02000e90e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555865997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2555865997
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3562722885
Short name T77
Test name
Test status
Simulation time 4646791656 ps
CPU time 28.03 seconds
Started Aug 06 04:36:55 PM PDT 24
Finished Aug 06 04:37:23 PM PDT 24
Peak memory 213860 kb
Host smart-6a34fcc4-3bfe-4372-ad5e-08f7cd1f96d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562722885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
562722885
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2989484610
Short name T47
Test name
Test status
Simulation time 9455689270 ps
CPU time 20.49 seconds
Started Aug 06 04:43:13 PM PDT 24
Finished Aug 06 04:43:33 PM PDT 24
Peak memory 205596 kb
Host smart-1a59d0f8-7a17-4865-a334-abc2e99b7961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989484610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2989484610
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.403724446
Short name T31
Test name
Test status
Simulation time 4621235107 ps
CPU time 13.49 seconds
Started Aug 06 04:43:13 PM PDT 24
Finished Aug 06 04:43:26 PM PDT 24
Peak memory 213608 kb
Host smart-0a5ed74b-27cb-4f9a-8b69-0d670a7a9476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403724446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.403724446
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.3370540903
Short name T9
Test name
Test status
Simulation time 291370624410 ps
CPU time 1101.84 seconds
Started Aug 06 04:43:10 PM PDT 24
Finished Aug 06 05:01:32 PM PDT 24
Peak memory 235560 kb
Host smart-f2d6e3b2-1027-4dff-9b74-94531eccc07d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370540903 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.3370540903
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.4046119367
Short name T46
Test name
Test status
Simulation time 379050877 ps
CPU time 0.89 seconds
Started Aug 06 04:43:08 PM PDT 24
Finished Aug 06 04:43:09 PM PDT 24
Peak memory 205164 kb
Host smart-a00b027b-41e7-4af1-a906-ed695832eab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046119367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.4046119367
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.521497563
Short name T42
Test name
Test status
Simulation time 1172030169 ps
CPU time 3.83 seconds
Started Aug 06 04:43:02 PM PDT 24
Finished Aug 06 04:43:06 PM PDT 24
Peak memory 229724 kb
Host smart-49691620-7185-45b6-9793-fbd77a4a1cc6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521497563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.521497563
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3914449218
Short name T87
Test name
Test status
Simulation time 386131029 ps
CPU time 2.53 seconds
Started Aug 06 04:36:31 PM PDT 24
Finished Aug 06 04:36:34 PM PDT 24
Peak memory 213648 kb
Host smart-8a620329-10c8-41d7-aba7-e5298a954337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914449218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3914449218
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2733558552
Short name T125
Test name
Test status
Simulation time 710236390 ps
CPU time 1.33 seconds
Started Aug 06 04:43:09 PM PDT 24
Finished Aug 06 04:43:11 PM PDT 24
Peak memory 205328 kb
Host smart-ad0e6ed7-f7f3-4693-a1b1-d7acaf26dc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733558552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2733558552
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.4151815806
Short name T6
Test name
Test status
Simulation time 132039376646 ps
CPU time 1127.49 seconds
Started Aug 06 04:43:13 PM PDT 24
Finished Aug 06 05:02:01 PM PDT 24
Peak memory 235496 kb
Host smart-18f300b8-d7e7-477a-88bc-c03e5566e89d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151815806 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.4151815806
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2813561564
Short name T126
Test name
Test status
Simulation time 34569659689 ps
CPU time 91.79 seconds
Started Aug 06 04:43:23 PM PDT 24
Finished Aug 06 04:44:55 PM PDT 24
Peak memory 213788 kb
Host smart-3f30d34a-9209-4062-a739-3ba2110f64c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813561564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2813561564
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4000104401
Short name T14
Test name
Test status
Simulation time 207146978 ps
CPU time 1.26 seconds
Started Aug 06 04:43:04 PM PDT 24
Finished Aug 06 04:43:05 PM PDT 24
Peak memory 204992 kb
Host smart-724f4bc3-094f-461e-a375-e247db04bed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000104401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4000104401
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1883521690
Short name T61
Test name
Test status
Simulation time 189441697 ps
CPU time 0.77 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:12 PM PDT 24
Peak memory 205172 kb
Host smart-112bdba3-8201-46ad-aaf7-ef226a22eefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883521690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1883521690
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1106491893
Short name T131
Test name
Test status
Simulation time 3498626459 ps
CPU time 9.68 seconds
Started Aug 06 04:43:19 PM PDT 24
Finished Aug 06 04:43:29 PM PDT 24
Peak memory 214912 kb
Host smart-638b9b80-a359-4013-906e-8d1cd7d1cfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106491893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1106491893
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2886263350
Short name T28
Test name
Test status
Simulation time 126839689 ps
CPU time 0.86 seconds
Started Aug 06 04:42:51 PM PDT 24
Finished Aug 06 04:42:52 PM PDT 24
Peak memory 213312 kb
Host smart-ea709602-1422-41b1-96e9-a2335a6a64c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886263350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2886263350
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1637786514
Short name T156
Test name
Test status
Simulation time 3357635308 ps
CPU time 16.79 seconds
Started Aug 06 04:36:56 PM PDT 24
Finished Aug 06 04:37:12 PM PDT 24
Peak memory 213952 kb
Host smart-3f56737a-edca-43d5-851b-204ad44a9fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637786514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
637786514
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.765052459
Short name T23
Test name
Test status
Simulation time 3153832283 ps
CPU time 8.93 seconds
Started Aug 06 04:43:12 PM PDT 24
Finished Aug 06 04:43:21 PM PDT 24
Peak memory 205592 kb
Host smart-9903a3dd-02de-4f98-8f89-dc0c294c7064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765052459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.765052459
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.2729051660
Short name T22
Test name
Test status
Simulation time 115996775 ps
CPU time 0.94 seconds
Started Aug 06 04:43:06 PM PDT 24
Finished Aug 06 04:43:07 PM PDT 24
Peak memory 205156 kb
Host smart-ef4be6ce-bb46-4bbd-9672-ad339db8d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729051660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2729051660
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3184083157
Short name T34
Test name
Test status
Simulation time 4216301079 ps
CPU time 12.87 seconds
Started Aug 06 04:42:52 PM PDT 24
Finished Aug 06 04:43:05 PM PDT 24
Peak memory 213612 kb
Host smart-7490dedb-acee-40ed-81a7-b53d5fb12e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184083157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3184083157
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.114034517
Short name T48
Test name
Test status
Simulation time 48830178764 ps
CPU time 232.97 seconds
Started Aug 06 04:36:04 PM PDT 24
Finished Aug 06 04:39:57 PM PDT 24
Peak memory 222020 kb
Host smart-5752726c-7be5-4dba-8e01-f94fc9b3fe2c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114034517 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.114034517
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.649994881
Short name T75
Test name
Test status
Simulation time 843674564 ps
CPU time 9.59 seconds
Started Aug 06 04:36:59 PM PDT 24
Finished Aug 06 04:37:08 PM PDT 24
Peak memory 213700 kb
Host smart-0b7dffa2-f43f-4e8c-9656-12be699d982b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649994881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.649994881
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1384501521
Short name T158
Test name
Test status
Simulation time 2637148761 ps
CPU time 14.27 seconds
Started Aug 06 04:36:58 PM PDT 24
Finished Aug 06 04:37:12 PM PDT 24
Peak memory 213832 kb
Host smart-9ded89f7-dea2-4662-a8c9-82735aec602a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384501521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
384501521
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1164402897
Short name T139
Test name
Test status
Simulation time 1361801462 ps
CPU time 2.17 seconds
Started Aug 06 04:42:57 PM PDT 24
Finished Aug 06 04:43:00 PM PDT 24
Peak memory 204800 kb
Host smart-3e6fdf0f-1948-4e3d-95cc-102245755a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164402897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1164402897
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.1879953016
Short name T19
Test name
Test status
Simulation time 3289110342 ps
CPU time 9.17 seconds
Started Aug 06 04:43:20 PM PDT 24
Finished Aug 06 04:43:29 PM PDT 24
Peak memory 205424 kb
Host smart-157dfbe3-6184-489d-baf8-8b9085b28228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879953016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1879953016
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.1677127582
Short name T16
Test name
Test status
Simulation time 5224049170 ps
CPU time 7.13 seconds
Started Aug 06 04:43:19 PM PDT 24
Finished Aug 06 04:43:26 PM PDT 24
Peak memory 213740 kb
Host smart-5787728c-bb85-411a-96e5-2ae5d4328724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677127582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1677127582
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1539269323
Short name T53
Test name
Test status
Simulation time 6906002841 ps
CPU time 6.6 seconds
Started Aug 06 04:36:09 PM PDT 24
Finished Aug 06 04:36:15 PM PDT 24
Peak memory 205444 kb
Host smart-61b41260-ceea-4261-924d-03799629ccd8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539269323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1539269323
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.505741459
Short name T39
Test name
Test status
Simulation time 148406947 ps
CPU time 1.15 seconds
Started Aug 06 04:43:03 PM PDT 24
Finished Aug 06 04:43:04 PM PDT 24
Peak memory 205128 kb
Host smart-9ba8ea79-0f18-4724-aa90-bb0f4c670676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505741459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.505741459
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2887531553
Short name T89
Test name
Test status
Simulation time 3107771070 ps
CPU time 5.06 seconds
Started Aug 06 04:36:08 PM PDT 24
Finished Aug 06 04:36:13 PM PDT 24
Peak memory 205572 kb
Host smart-890b497b-07d7-4ad6-ba94-d5b7f176b29e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887531553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2887531553
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1428643747
Short name T79
Test name
Test status
Simulation time 389374367 ps
CPU time 6.63 seconds
Started Aug 06 04:36:37 PM PDT 24
Finished Aug 06 04:36:44 PM PDT 24
Peak memory 205460 kb
Host smart-e226686a-596b-493d-90bc-6edc75f1e3a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428643747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1428643747
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.216583651
Short name T25
Test name
Test status
Simulation time 675964036 ps
CPU time 1.75 seconds
Started Aug 06 04:43:04 PM PDT 24
Finished Aug 06 04:43:05 PM PDT 24
Peak memory 204976 kb
Host smart-cab86476-4ccb-46d6-b30b-be83a00760d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216583651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.216583651
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2827470537
Short name T130
Test name
Test status
Simulation time 2218190763 ps
CPU time 3.28 seconds
Started Aug 06 04:43:03 PM PDT 24
Finished Aug 06 04:43:07 PM PDT 24
Peak memory 221972 kb
Host smart-7f79cf24-cca7-444c-b85e-358515088986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827470537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2827470537
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2019838116
Short name T136
Test name
Test status
Simulation time 1081535578 ps
CPU time 1.94 seconds
Started Aug 06 04:43:26 PM PDT 24
Finished Aug 06 04:43:28 PM PDT 24
Peak memory 205448 kb
Host smart-dfda6b4f-8035-49ce-aece-d68311830de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019838116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2019838116
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2557599221
Short name T97
Test name
Test status
Simulation time 172351633 ps
CPU time 1.59 seconds
Started Aug 06 04:37:01 PM PDT 24
Finished Aug 06 04:37:02 PM PDT 24
Peak memory 213684 kb
Host smart-89581453-29af-44e4-9a59-ba7798b8b3a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557599221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2557599221
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2105923417
Short name T321
Test name
Test status
Simulation time 2283314641 ps
CPU time 24.49 seconds
Started Aug 06 04:36:08 PM PDT 24
Finished Aug 06 04:36:33 PM PDT 24
Peak memory 205512 kb
Host smart-af7f2c47-f017-4df5-b9da-5b013ef98320
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105923417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2105923417
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1787960546
Short name T465
Test name
Test status
Simulation time 5684256073 ps
CPU time 34.91 seconds
Started Aug 06 04:36:03 PM PDT 24
Finished Aug 06 04:36:38 PM PDT 24
Peak memory 213788 kb
Host smart-8706207c-8797-4989-bab7-b8bfd035dc48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787960546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1787960546
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1286487796
Short name T399
Test name
Test status
Simulation time 931167681 ps
CPU time 3.96 seconds
Started Aug 06 04:36:16 PM PDT 24
Finished Aug 06 04:36:20 PM PDT 24
Peak memory 219020 kb
Host smart-71c7f06d-15f3-4a19-8354-1236a8975ad0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286487796 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1286487796
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1078396672
Short name T106
Test name
Test status
Simulation time 211763908 ps
CPU time 2.37 seconds
Started Aug 06 04:36:15 PM PDT 24
Finished Aug 06 04:36:18 PM PDT 24
Peak memory 213592 kb
Host smart-b72744ec-0fcb-4cec-8b64-dffa25ad6126
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078396672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1078396672
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1824296343
Short name T337
Test name
Test status
Simulation time 18971475975 ps
CPU time 18.1 seconds
Started Aug 06 04:36:09 PM PDT 24
Finished Aug 06 04:36:27 PM PDT 24
Peak memory 205464 kb
Host smart-72e835d4-b4fd-45e8-a2f0-9cfb27285225
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824296343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1824296343
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2275332794
Short name T323
Test name
Test status
Simulation time 5730549179 ps
CPU time 3.61 seconds
Started Aug 06 04:36:08 PM PDT 24
Finished Aug 06 04:36:11 PM PDT 24
Peak memory 205388 kb
Host smart-6358e4d0-602f-46bb-a45c-d3f4e7588688
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275332794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2275332794
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1095953609
Short name T454
Test name
Test status
Simulation time 1918446182 ps
CPU time 3.84 seconds
Started Aug 06 04:36:09 PM PDT 24
Finished Aug 06 04:36:13 PM PDT 24
Peak memory 205304 kb
Host smart-3f5de569-930f-4c26-b883-ef56198dc327
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095953609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
095953609
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2939944718
Short name T367
Test name
Test status
Simulation time 1145701347 ps
CPU time 3.47 seconds
Started Aug 06 04:36:05 PM PDT 24
Finished Aug 06 04:36:09 PM PDT 24
Peak memory 205200 kb
Host smart-2bcfedc2-b847-4a90-9f1b-626c92ababe8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939944718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2939944718
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2614604683
Short name T361
Test name
Test status
Simulation time 213625653 ps
CPU time 1.21 seconds
Started Aug 06 04:36:05 PM PDT 24
Finished Aug 06 04:36:06 PM PDT 24
Peak memory 205292 kb
Host smart-c892fe4c-2272-4f81-9af0-71758a702dae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614604683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2614604683
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3200788799
Short name T353
Test name
Test status
Simulation time 484898526 ps
CPU time 1.19 seconds
Started Aug 06 04:36:09 PM PDT 24
Finished Aug 06 04:36:10 PM PDT 24
Peak memory 205228 kb
Host smart-b6a4ce82-813f-4172-b976-dd1687b83aaf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200788799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
200788799
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1378153310
Short name T432
Test name
Test status
Simulation time 29681665 ps
CPU time 0.79 seconds
Started Aug 06 04:36:08 PM PDT 24
Finished Aug 06 04:36:08 PM PDT 24
Peak memory 205212 kb
Host smart-cc64e0e1-d505-4023-a147-fb635e58bde1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378153310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1378153310
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.913620
Short name T309
Test name
Test status
Simulation time 126116367 ps
CPU time 0.82 seconds
Started Aug 06 04:36:05 PM PDT 24
Finished Aug 06 04:36:05 PM PDT 24
Peak memory 205124 kb
Host smart-5a85d09c-0a9f-4db6-a9c8-723c22aff266
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.913620
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3006805839
Short name T338
Test name
Test status
Simulation time 551833626 ps
CPU time 3.71 seconds
Started Aug 06 04:36:09 PM PDT 24
Finished Aug 06 04:36:13 PM PDT 24
Peak memory 213800 kb
Host smart-00b6ea9b-986a-452c-84fd-e832fa271cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006805839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3006805839
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1610506795
Short name T159
Test name
Test status
Simulation time 1488213852 ps
CPU time 10.72 seconds
Started Aug 06 04:36:09 PM PDT 24
Finished Aug 06 04:36:20 PM PDT 24
Peak memory 213676 kb
Host smart-79f44c36-cda0-4051-a35d-0bbb6c38d1bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610506795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1610506795
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3365192194
Short name T418
Test name
Test status
Simulation time 2133340470 ps
CPU time 30.75 seconds
Started Aug 06 04:36:33 PM PDT 24
Finished Aug 06 04:37:09 PM PDT 24
Peak memory 213576 kb
Host smart-2f248af5-c5a4-4bba-8900-a79ed906b55d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365192194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3365192194
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1373122113
Short name T341
Test name
Test status
Simulation time 26258424232 ps
CPU time 42.47 seconds
Started Aug 06 04:36:19 PM PDT 24
Finished Aug 06 04:37:02 PM PDT 24
Peak memory 213732 kb
Host smart-3d41cbd5-356c-4b33-979b-6c9cfa45ac9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373122113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1373122113
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1664111089
Short name T78
Test name
Test status
Simulation time 547367532 ps
CPU time 2.47 seconds
Started Aug 06 04:36:33 PM PDT 24
Finished Aug 06 04:36:36 PM PDT 24
Peak memory 213604 kb
Host smart-e986489e-4b1a-4e1c-bb34-e2faba3780be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664111089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1664111089
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1441420117
Short name T329
Test name
Test status
Simulation time 379805814 ps
CPU time 3.89 seconds
Started Aug 06 04:36:24 PM PDT 24
Finished Aug 06 04:36:28 PM PDT 24
Peak memory 218188 kb
Host smart-38ef6000-4ce3-45f8-b39d-310356117252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441420117 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1441420117
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2781135187
Short name T105
Test name
Test status
Simulation time 643760839 ps
CPU time 1.65 seconds
Started Aug 06 04:36:19 PM PDT 24
Finished Aug 06 04:36:21 PM PDT 24
Peak memory 213668 kb
Host smart-388ac7ad-2faf-48d3-b810-ee54baf56cf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781135187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2781135187
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3717133789
Short name T346
Test name
Test status
Simulation time 90659213048 ps
CPU time 73.64 seconds
Started Aug 06 04:36:37 PM PDT 24
Finished Aug 06 04:37:50 PM PDT 24
Peak memory 205524 kb
Host smart-ebeda06d-5f63-4e95-a29a-228cf89e025c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717133789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3717133789
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3401046083
Short name T364
Test name
Test status
Simulation time 14740293169 ps
CPU time 20.04 seconds
Started Aug 06 04:36:16 PM PDT 24
Finished Aug 06 04:36:36 PM PDT 24
Peak memory 205484 kb
Host smart-16142b8b-71f2-46b6-bc0f-ae8a935eaa82
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401046083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3401046083
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.618624862
Short name T92
Test name
Test status
Simulation time 8245368625 ps
CPU time 13.53 seconds
Started Aug 06 04:36:23 PM PDT 24
Finished Aug 06 04:36:36 PM PDT 24
Peak memory 205520 kb
Host smart-c967cf86-fda8-4bfb-8c3f-70c1326cdc5c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618624862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.618624862
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1107040174
Short name T306
Test name
Test status
Simulation time 1225828461 ps
CPU time 2.55 seconds
Started Aug 06 04:36:27 PM PDT 24
Finished Aug 06 04:36:29 PM PDT 24
Peak memory 205404 kb
Host smart-f17e24a6-a386-4646-9cf9-8965d9680c55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107040174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
107040174
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1934200601
Short name T449
Test name
Test status
Simulation time 928122397 ps
CPU time 1.33 seconds
Started Aug 06 04:36:39 PM PDT 24
Finished Aug 06 04:36:40 PM PDT 24
Peak memory 205108 kb
Host smart-e8f31c6c-cfa0-44fd-965f-ef65b5a4d1c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934200601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1934200601
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.441779242
Short name T330
Test name
Test status
Simulation time 19411702741 ps
CPU time 7.43 seconds
Started Aug 06 04:36:17 PM PDT 24
Finished Aug 06 04:36:25 PM PDT 24
Peak memory 205444 kb
Host smart-a924df9c-89a9-44fe-9c27-19d5441a7e1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441779242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.441779242
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1528925733
Short name T405
Test name
Test status
Simulation time 275393371 ps
CPU time 0.94 seconds
Started Aug 06 04:36:22 PM PDT 24
Finished Aug 06 04:36:23 PM PDT 24
Peak memory 205288 kb
Host smart-f14fec02-991f-4edc-9b6e-4f3d1ccbf88f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528925733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1528925733
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1349984217
Short name T375
Test name
Test status
Simulation time 541883068 ps
CPU time 1.14 seconds
Started Aug 06 04:36:27 PM PDT 24
Finished Aug 06 04:36:28 PM PDT 24
Peak memory 205212 kb
Host smart-018f361a-95a2-48d1-a5b6-fbdf761fce8d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349984217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
349984217
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1024186450
Short name T352
Test name
Test status
Simulation time 60957984 ps
CPU time 0.83 seconds
Started Aug 06 04:36:38 PM PDT 24
Finished Aug 06 04:36:39 PM PDT 24
Peak memory 205296 kb
Host smart-bb70a580-d4c4-4a09-b732-9694a617de13
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024186450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1024186450
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.942830736
Short name T308
Test name
Test status
Simulation time 61968099 ps
CPU time 0.81 seconds
Started Aug 06 04:36:19 PM PDT 24
Finished Aug 06 04:36:21 PM PDT 24
Peak memory 205164 kb
Host smart-74cb117e-99e1-435d-b699-6fb0cf18fe31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942830736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.942830736
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3443770163
Short name T451
Test name
Test status
Simulation time 289358091 ps
CPU time 4.37 seconds
Started Aug 06 04:36:19 PM PDT 24
Finished Aug 06 04:36:24 PM PDT 24
Peak memory 205476 kb
Host smart-53afa20b-fd03-4618-a1c4-0dc21c240521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443770163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3443770163
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3377836889
Short name T161
Test name
Test status
Simulation time 32665283276 ps
CPU time 10.57 seconds
Started Aug 06 04:36:38 PM PDT 24
Finished Aug 06 04:36:49 PM PDT 24
Peak memory 216288 kb
Host smart-d415c7cd-1dd5-4290-85ff-091cc07cf812
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377836889 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3377836889
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3437826167
Short name T115
Test name
Test status
Simulation time 257479418 ps
CPU time 4.86 seconds
Started Aug 06 04:36:21 PM PDT 24
Finished Aug 06 04:36:26 PM PDT 24
Peak memory 213776 kb
Host smart-083253c5-a042-4daf-93bf-31429549aebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437826167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3437826167
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3473202828
Short name T392
Test name
Test status
Simulation time 2568617730 ps
CPU time 9.73 seconds
Started Aug 06 04:36:40 PM PDT 24
Finished Aug 06 04:36:50 PM PDT 24
Peak memory 213792 kb
Host smart-00d2aaf3-7f8c-4ec8-b053-8bd77364e274
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473202828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3473202828
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3730482201
Short name T313
Test name
Test status
Simulation time 568303113 ps
CPU time 3.74 seconds
Started Aug 06 04:36:50 PM PDT 24
Finished Aug 06 04:36:53 PM PDT 24
Peak memory 219792 kb
Host smart-7da12d3d-8fd8-427f-9647-65c5a955ed22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730482201 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3730482201
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2219322995
Short name T331
Test name
Test status
Simulation time 211223495 ps
CPU time 1.51 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:36:53 PM PDT 24
Peak memory 213556 kb
Host smart-5b7f8a64-91b0-4c0f-89fe-576fa68fefb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219322995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2219322995
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3512622133
Short name T433
Test name
Test status
Simulation time 8017327422 ps
CPU time 10.33 seconds
Started Aug 06 04:36:43 PM PDT 24
Finished Aug 06 04:36:53 PM PDT 24
Peak memory 205484 kb
Host smart-867d600d-ad42-4101-a8cc-19328de95936
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512622133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3512622133
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2835690919
Short name T461
Test name
Test status
Simulation time 5049319349 ps
CPU time 7.87 seconds
Started Aug 06 04:36:37 PM PDT 24
Finished Aug 06 04:36:45 PM PDT 24
Peak memory 205460 kb
Host smart-45888f8f-1cf8-41f3-ac37-3a84a4455242
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835690919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2835690919
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.632415251
Short name T398
Test name
Test status
Simulation time 416929191 ps
CPU time 0.93 seconds
Started Aug 06 04:36:38 PM PDT 24
Finished Aug 06 04:36:39 PM PDT 24
Peak memory 205144 kb
Host smart-78408ab8-48ec-4b85-8f21-3e56ada87d10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632415251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.632415251
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4287424607
Short name T95
Test name
Test status
Simulation time 539346882 ps
CPU time 7.37 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:37:02 PM PDT 24
Peak memory 205480 kb
Host smart-f588737d-dce1-4044-ac44-0950dd798b32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287424607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.4287424607
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4158447739
Short name T344
Test name
Test status
Simulation time 506467661 ps
CPU time 5.08 seconds
Started Aug 06 04:36:53 PM PDT 24
Finished Aug 06 04:36:58 PM PDT 24
Peak memory 213732 kb
Host smart-0785dc45-aac9-4951-896a-124b2df72a8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158447739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4158447739
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.47930204
Short name T354
Test name
Test status
Simulation time 98987504 ps
CPU time 4.22 seconds
Started Aug 06 04:36:52 PM PDT 24
Finished Aug 06 04:36:57 PM PDT 24
Peak memory 220308 kb
Host smart-7479e3c4-a406-46c1-8f4a-1c8e72e8c252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47930204 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.47930204
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3036232013
Short name T385
Test name
Test status
Simulation time 231213827 ps
CPU time 1.56 seconds
Started Aug 06 04:36:40 PM PDT 24
Finished Aug 06 04:36:41 PM PDT 24
Peak memory 213648 kb
Host smart-d0e53265-503b-48ed-9267-df17e3d5cbd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036232013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3036232013
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.876077257
Short name T314
Test name
Test status
Simulation time 5338044734 ps
CPU time 4.47 seconds
Started Aug 06 04:36:55 PM PDT 24
Finished Aug 06 04:37:00 PM PDT 24
Peak memory 205432 kb
Host smart-08eb8211-d297-4765-b96e-0063d6b33fa1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876077257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
rv_dm_jtag_dmi_csr_bit_bash.876077257
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2610129
Short name T373
Test name
Test status
Simulation time 5455305586 ps
CPU time 14.59 seconds
Started Aug 06 04:36:36 PM PDT 24
Finished Aug 06 04:36:51 PM PDT 24
Peak memory 205496 kb
Host smart-5222e98d-5cfb-456d-991d-d7744919fc8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.2610129
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1045601095
Short name T52
Test name
Test status
Simulation time 677201689 ps
CPU time 1.12 seconds
Started Aug 06 04:36:36 PM PDT 24
Finished Aug 06 04:36:37 PM PDT 24
Peak memory 205196 kb
Host smart-112193fb-c01e-46fd-94ab-d0ccd3ad9ed8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045601095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1045601095
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1132559432
Short name T109
Test name
Test status
Simulation time 1151911815 ps
CPU time 4.4 seconds
Started Aug 06 04:36:57 PM PDT 24
Finished Aug 06 04:37:01 PM PDT 24
Peak memory 205496 kb
Host smart-94ee4c15-82c2-4d17-9f04-ff9f368dc65b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132559432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1132559432
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3991688345
Short name T381
Test name
Test status
Simulation time 78579011 ps
CPU time 2.95 seconds
Started Aug 06 04:36:56 PM PDT 24
Finished Aug 06 04:36:59 PM PDT 24
Peak memory 216324 kb
Host smart-26512517-4933-4756-bac5-03d02194dacb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991688345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3991688345
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.282214122
Short name T160
Test name
Test status
Simulation time 1333329162 ps
CPU time 10.83 seconds
Started Aug 06 04:36:53 PM PDT 24
Finished Aug 06 04:37:04 PM PDT 24
Peak memory 213700 kb
Host smart-27bc8498-441a-4515-9aa4-159a85cf026c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282214122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.282214122
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.955553515
Short name T417
Test name
Test status
Simulation time 358816869 ps
CPU time 2.23 seconds
Started Aug 06 04:36:50 PM PDT 24
Finished Aug 06 04:36:52 PM PDT 24
Peak memory 216384 kb
Host smart-2fcbf80f-a666-49fc-86f3-9a5223c277d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955553515 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.955553515
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.789603312
Short name T439
Test name
Test status
Simulation time 71364767 ps
CPU time 1.38 seconds
Started Aug 06 04:36:39 PM PDT 24
Finished Aug 06 04:36:41 PM PDT 24
Peak memory 213528 kb
Host smart-4fb16155-c70c-418f-bc04-472b353b0eef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789603312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.789603312
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3733649935
Short name T343
Test name
Test status
Simulation time 3733160152 ps
CPU time 2.03 seconds
Started Aug 06 04:36:36 PM PDT 24
Finished Aug 06 04:36:38 PM PDT 24
Peak memory 205496 kb
Host smart-6b170f7c-edad-43e7-9660-241262b42ce3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733649935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3733649935
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1883712980
Short name T458
Test name
Test status
Simulation time 4498738830 ps
CPU time 4.18 seconds
Started Aug 06 04:36:52 PM PDT 24
Finished Aug 06 04:36:57 PM PDT 24
Peak memory 205420 kb
Host smart-f0754423-c328-4608-9c0c-356ed2601705
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883712980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1883712980
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3198956507
Short name T406
Test name
Test status
Simulation time 288333006 ps
CPU time 1.21 seconds
Started Aug 06 04:36:52 PM PDT 24
Finished Aug 06 04:36:53 PM PDT 24
Peak memory 205104 kb
Host smart-cd1705e3-e502-4700-baf5-177e45394911
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198956507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3198956507
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1145891983
Short name T82
Test name
Test status
Simulation time 887852938 ps
CPU time 8.34 seconds
Started Aug 06 04:36:50 PM PDT 24
Finished Aug 06 04:36:59 PM PDT 24
Peak memory 204876 kb
Host smart-9020d453-1a43-40eb-bf6d-9bdc43900c72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145891983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1145891983
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.659037377
Short name T464
Test name
Test status
Simulation time 514417709 ps
CPU time 3 seconds
Started Aug 06 04:36:52 PM PDT 24
Finished Aug 06 04:36:55 PM PDT 24
Peak memory 213712 kb
Host smart-a35fe9a8-3578-48e7-8547-f27a621aadc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659037377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.659037377
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3951656797
Short name T420
Test name
Test status
Simulation time 16650404996 ps
CPU time 27.43 seconds
Started Aug 06 04:36:40 PM PDT 24
Finished Aug 06 04:37:07 PM PDT 24
Peak memory 214416 kb
Host smart-af839a4b-d4d6-41d2-8127-dcbb9cbb5d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951656797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
951656797
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1491405857
Short name T442
Test name
Test status
Simulation time 512953228 ps
CPU time 4.39 seconds
Started Aug 06 04:36:39 PM PDT 24
Finished Aug 06 04:36:43 PM PDT 24
Peak memory 221964 kb
Host smart-10d2a8cb-e21a-475e-83d2-e8c1f01bad0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491405857 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1491405857
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.256534448
Short name T86
Test name
Test status
Simulation time 127736989 ps
CPU time 2.55 seconds
Started Aug 06 04:36:39 PM PDT 24
Finished Aug 06 04:36:42 PM PDT 24
Peak memory 213596 kb
Host smart-f9d3f0cc-1b99-4ed6-83b4-8409d891c8e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256534448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.256534448
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3647492338
Short name T363
Test name
Test status
Simulation time 8522212214 ps
CPU time 7.02 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:36:58 PM PDT 24
Peak memory 205424 kb
Host smart-107afa56-269a-46e1-b86c-1790c5f6a3ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647492338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3647492338
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2308232729
Short name T409
Test name
Test status
Simulation time 11833131659 ps
CPU time 8.38 seconds
Started Aug 06 04:36:40 PM PDT 24
Finished Aug 06 04:36:48 PM PDT 24
Peak memory 205376 kb
Host smart-2fb7b8cd-f29c-4c1f-9f03-326c5303575a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308232729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2308232729
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3426821295
Short name T397
Test name
Test status
Simulation time 319804063 ps
CPU time 0.75 seconds
Started Aug 06 04:36:40 PM PDT 24
Finished Aug 06 04:36:41 PM PDT 24
Peak memory 205200 kb
Host smart-46cfbd11-fced-4afb-95db-5348eb57777d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426821295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3426821295
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2615369036
Short name T382
Test name
Test status
Simulation time 1343345013 ps
CPU time 7.76 seconds
Started Aug 06 04:36:53 PM PDT 24
Finished Aug 06 04:37:01 PM PDT 24
Peak memory 205480 kb
Host smart-2515d131-f3fb-418a-aef5-b6d74bd693d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615369036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2615369036
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.377077947
Short name T370
Test name
Test status
Simulation time 268784572 ps
CPU time 5.04 seconds
Started Aug 06 04:36:40 PM PDT 24
Finished Aug 06 04:36:45 PM PDT 24
Peak memory 213652 kb
Host smart-410ee6e5-4926-4981-9a93-49bc0c52cd98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377077947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.377077947
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2333246132
Short name T88
Test name
Test status
Simulation time 1007822836 ps
CPU time 11.48 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:37:03 PM PDT 24
Peak memory 213048 kb
Host smart-f1c992e3-b086-4d1a-b1d2-f7c716c40a74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333246132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
333246132
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.154762785
Short name T112
Test name
Test status
Simulation time 333791247 ps
CPU time 3.81 seconds
Started Aug 06 04:36:52 PM PDT 24
Finished Aug 06 04:36:56 PM PDT 24
Peak memory 219304 kb
Host smart-6ba89fd6-8246-465f-b202-86f68103c89d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154762785 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.154762785
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1023054215
Short name T98
Test name
Test status
Simulation time 291470427 ps
CPU time 2.45 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:36:54 PM PDT 24
Peak memory 213644 kb
Host smart-8ec077d3-1aac-40b6-a4cd-f5d4c717ebf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023054215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1023054215
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3212471239
Short name T380
Test name
Test status
Simulation time 10390332634 ps
CPU time 17.82 seconds
Started Aug 06 04:36:57 PM PDT 24
Finished Aug 06 04:37:15 PM PDT 24
Peak memory 205460 kb
Host smart-830071ce-d931-46c8-acd4-9337fdd3cab0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212471239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3212471239
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2021892949
Short name T401
Test name
Test status
Simulation time 2292967115 ps
CPU time 7.87 seconds
Started Aug 06 04:36:40 PM PDT 24
Finished Aug 06 04:36:48 PM PDT 24
Peak memory 205376 kb
Host smart-0033e1e2-87c0-4a88-88ee-3a507d537e78
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021892949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2021892949
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.815900917
Short name T351
Test name
Test status
Simulation time 256299632 ps
CPU time 1.38 seconds
Started Aug 06 04:36:57 PM PDT 24
Finished Aug 06 04:36:58 PM PDT 24
Peak memory 205120 kb
Host smart-b7b31358-14f4-46fd-893d-0f8103c4b7fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815900917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.815900917
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2378311689
Short name T101
Test name
Test status
Simulation time 298071710 ps
CPU time 3.59 seconds
Started Aug 06 04:36:52 PM PDT 24
Finished Aug 06 04:36:55 PM PDT 24
Peak memory 205600 kb
Host smart-366e5838-07a6-45c0-b380-f43b525dfea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378311689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2378311689
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.966415249
Short name T311
Test name
Test status
Simulation time 519920154 ps
CPU time 5.62 seconds
Started Aug 06 04:36:49 PM PDT 24
Finished Aug 06 04:36:55 PM PDT 24
Peak memory 213796 kb
Host smart-45d77f5b-cdfe-41b6-b3fc-95852999722e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966415249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.966415249
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1813676495
Short name T315
Test name
Test status
Simulation time 178912513 ps
CPU time 2.64 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:36:56 PM PDT 24
Peak memory 219352 kb
Host smart-598c3dae-87fc-432b-9940-661b4ac82ddc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813676495 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1813676495
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.192249012
Short name T441
Test name
Test status
Simulation time 710306249 ps
CPU time 2.24 seconds
Started Aug 06 04:36:49 PM PDT 24
Finished Aug 06 04:36:52 PM PDT 24
Peak memory 213708 kb
Host smart-2bf34630-7c74-4411-9897-aec0146ba3f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192249012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.192249012
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3093233642
Short name T384
Test name
Test status
Simulation time 20359089055 ps
CPU time 58.12 seconds
Started Aug 06 04:36:49 PM PDT 24
Finished Aug 06 04:37:47 PM PDT 24
Peak memory 205408 kb
Host smart-8e5da06f-8ecf-493b-b62d-6cc525adfb08
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093233642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3093233642
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.101044259
Short name T349
Test name
Test status
Simulation time 1421081466 ps
CPU time 1.81 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:36:53 PM PDT 24
Peak memory 205336 kb
Host smart-6617ea1d-f47d-4066-aec3-9ffda3badfd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101044259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.101044259
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3232213565
Short name T326
Test name
Test status
Simulation time 259157257 ps
CPU time 0.96 seconds
Started Aug 06 04:37:05 PM PDT 24
Finished Aug 06 04:37:06 PM PDT 24
Peak memory 205160 kb
Host smart-86a7ade5-c305-430b-b20c-1e2d00743704
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232213565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3232213565
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.703450581
Short name T450
Test name
Test status
Simulation time 893411750 ps
CPU time 7.71 seconds
Started Aug 06 04:36:50 PM PDT 24
Finished Aug 06 04:36:58 PM PDT 24
Peak memory 205912 kb
Host smart-1e3057de-d3be-48f9-955c-cc82785baa15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703450581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.703450581
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.631320197
Short name T312
Test name
Test status
Simulation time 351331888 ps
CPU time 5.74 seconds
Started Aug 06 04:36:56 PM PDT 24
Finished Aug 06 04:37:01 PM PDT 24
Peak memory 213740 kb
Host smart-9819b6f9-bdd0-4410-bd8a-4c72eefdfbd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631320197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.631320197
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.265907725
Short name T444
Test name
Test status
Simulation time 1360178824 ps
CPU time 17.81 seconds
Started Aug 06 04:36:49 PM PDT 24
Finished Aug 06 04:37:07 PM PDT 24
Peak memory 213716 kb
Host smart-a4d3fc08-f318-4839-b8e6-6933c7d39c0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265907725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.265907725
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3915744356
Short name T387
Test name
Test status
Simulation time 276360850 ps
CPU time 4.58 seconds
Started Aug 06 04:36:57 PM PDT 24
Finished Aug 06 04:37:02 PM PDT 24
Peak memory 219724 kb
Host smart-3c3f71ca-6104-434e-b8a1-44c3e2039764
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915744356 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3915744356
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2888197211
Short name T422
Test name
Test status
Simulation time 187771087 ps
CPU time 2.38 seconds
Started Aug 06 04:36:58 PM PDT 24
Finished Aug 06 04:37:00 PM PDT 24
Peak memory 213648 kb
Host smart-0114669f-49ae-468c-a772-d78c28fc13f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888197211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2888197211
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3165668150
Short name T452
Test name
Test status
Simulation time 28258908006 ps
CPU time 7.17 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:36:58 PM PDT 24
Peak memory 205552 kb
Host smart-bd7a4df4-e7c5-4b9f-b1f9-738bbae5a3ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165668150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.3165668150
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1627601344
Short name T304
Test name
Test status
Simulation time 7225147828 ps
CPU time 9.97 seconds
Started Aug 06 04:36:55 PM PDT 24
Finished Aug 06 04:37:05 PM PDT 24
Peak memory 205468 kb
Host smart-88643e88-96ed-4b55-9de7-336f3d4c45a6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627601344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1627601344
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.310753801
Short name T332
Test name
Test status
Simulation time 545122809 ps
CPU time 0.82 seconds
Started Aug 06 04:36:55 PM PDT 24
Finished Aug 06 04:36:56 PM PDT 24
Peak memory 205168 kb
Host smart-aff97b46-c681-4953-963b-8ffe52bf1b83
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310753801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.310753801
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1911138979
Short name T108
Test name
Test status
Simulation time 183768087 ps
CPU time 6.41 seconds
Started Aug 06 04:37:03 PM PDT 24
Finished Aug 06 04:37:09 PM PDT 24
Peak memory 205420 kb
Host smart-fb8caed1-b65f-4bd0-80ee-e9b2bc73ee54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911138979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1911138979
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1355623947
Short name T391
Test name
Test status
Simulation time 266763282 ps
CPU time 3.3 seconds
Started Aug 06 04:36:58 PM PDT 24
Finished Aug 06 04:37:01 PM PDT 24
Peak memory 213764 kb
Host smart-a97c694d-db38-40a0-9fa2-30ba7f91f2fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355623947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1355623947
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4038013641
Short name T310
Test name
Test status
Simulation time 101144992 ps
CPU time 2.56 seconds
Started Aug 06 04:37:05 PM PDT 24
Finished Aug 06 04:37:07 PM PDT 24
Peak memory 221840 kb
Host smart-f09039c4-c2e5-42dc-bb65-0a20b0e3f0f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038013641 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4038013641
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3078718733
Short name T81
Test name
Test status
Simulation time 113154702 ps
CPU time 1.73 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:36:56 PM PDT 24
Peak memory 213648 kb
Host smart-8fe9b48a-5af9-4eca-b2cf-13f43eac6af1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078718733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3078718733
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1234385566
Short name T355
Test name
Test status
Simulation time 10491040272 ps
CPU time 9.03 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:37:03 PM PDT 24
Peak memory 205440 kb
Host smart-e14e79d2-f8af-4bcc-8147-264e35c9f678
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234385566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1234385566
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.528537010
Short name T390
Test name
Test status
Simulation time 2011358772 ps
CPU time 3.48 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:36:58 PM PDT 24
Peak memory 205344 kb
Host smart-6876a733-c28a-4a16-868b-9215f1cf616d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528537010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.528537010
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1313959194
Short name T457
Test name
Test status
Simulation time 802162509 ps
CPU time 1.09 seconds
Started Aug 06 04:36:56 PM PDT 24
Finished Aug 06 04:36:57 PM PDT 24
Peak memory 205140 kb
Host smart-d09dcef0-accb-4dec-91cf-6057ef28563f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313959194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1313959194
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.253339433
Short name T107
Test name
Test status
Simulation time 170068313 ps
CPU time 6.67 seconds
Started Aug 06 04:37:00 PM PDT 24
Finished Aug 06 04:37:07 PM PDT 24
Peak memory 205512 kb
Host smart-fe89d4cf-e979-49b2-8cbb-805eab49cf1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253339433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.253339433
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3988415616
Short name T76
Test name
Test status
Simulation time 121293479 ps
CPU time 5.17 seconds
Started Aug 06 04:36:55 PM PDT 24
Finished Aug 06 04:37:05 PM PDT 24
Peak memory 213692 kb
Host smart-6da57f1c-b9cc-42b3-8398-38c4a677f73a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988415616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3988415616
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1192882224
Short name T425
Test name
Test status
Simulation time 3004343412 ps
CPU time 21.35 seconds
Started Aug 06 04:36:53 PM PDT 24
Finished Aug 06 04:37:14 PM PDT 24
Peak memory 213876 kb
Host smart-3640b866-ddc2-4898-9b3b-c525d1243f81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192882224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
192882224
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1886066789
Short name T388
Test name
Test status
Simulation time 329357273 ps
CPU time 2.35 seconds
Started Aug 06 04:36:59 PM PDT 24
Finished Aug 06 04:37:01 PM PDT 24
Peak memory 218176 kb
Host smart-cedf4d13-ada3-43f4-95f1-b05a88d38179
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886066789 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1886066789
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2362984640
Short name T103
Test name
Test status
Simulation time 169806670 ps
CPU time 2.41 seconds
Started Aug 06 04:36:57 PM PDT 24
Finished Aug 06 04:37:00 PM PDT 24
Peak memory 213596 kb
Host smart-e90566d1-078b-4a10-ba77-cb7e5eb14a78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362984640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2362984640
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3649025236
Short name T342
Test name
Test status
Simulation time 32949092 ps
CPU time 0.7 seconds
Started Aug 06 04:36:50 PM PDT 24
Finished Aug 06 04:36:51 PM PDT 24
Peak memory 205128 kb
Host smart-78d7398a-c038-44ab-a819-d5b25b1f7fa9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649025236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.3649025236
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2991851100
Short name T466
Test name
Test status
Simulation time 1521948427 ps
CPU time 1.9 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:36:53 PM PDT 24
Peak memory 205320 kb
Host smart-60946f82-ae7b-4423-a26d-0dd4395ebd5c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991851100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2991851100
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1779647333
Short name T317
Test name
Test status
Simulation time 110394856 ps
CPU time 0.94 seconds
Started Aug 06 04:36:53 PM PDT 24
Finished Aug 06 04:36:54 PM PDT 24
Peak memory 205184 kb
Host smart-a4eecfb6-5b41-41ec-b823-4d38dc3762b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779647333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1779647333
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.104018596
Short name T435
Test name
Test status
Simulation time 231678208 ps
CPU time 4 seconds
Started Aug 06 04:36:59 PM PDT 24
Finished Aug 06 04:37:03 PM PDT 24
Peak memory 205424 kb
Host smart-7809e487-2eda-43c1-a759-08b4fd01f321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104018596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.104018596
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1834777154
Short name T322
Test name
Test status
Simulation time 322536124 ps
CPU time 2.95 seconds
Started Aug 06 04:37:01 PM PDT 24
Finished Aug 06 04:37:04 PM PDT 24
Peak memory 213680 kb
Host smart-ea3096fa-ed6b-4d0e-933d-b2c7fbe337e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834777154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1834777154
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.101260854
Short name T413
Test name
Test status
Simulation time 408842389 ps
CPU time 4.73 seconds
Started Aug 06 04:37:00 PM PDT 24
Finished Aug 06 04:37:05 PM PDT 24
Peak memory 221876 kb
Host smart-f05839ed-9cb6-4072-a020-a90f42912821
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101260854 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.101260854
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.616496450
Short name T428
Test name
Test status
Simulation time 96921196 ps
CPU time 1.63 seconds
Started Aug 06 04:36:57 PM PDT 24
Finished Aug 06 04:36:59 PM PDT 24
Peak memory 213708 kb
Host smart-7cf1c7de-ec58-4bf1-b5e5-92463487cb75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616496450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.616496450
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1768467573
Short name T440
Test name
Test status
Simulation time 15606606525 ps
CPU time 43.31 seconds
Started Aug 06 04:37:01 PM PDT 24
Finished Aug 06 04:37:45 PM PDT 24
Peak memory 205532 kb
Host smart-37bb47d2-f16f-412a-9e7a-51548168ea8a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768467573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.1768467573
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2504100284
Short name T429
Test name
Test status
Simulation time 2906108082 ps
CPU time 3.16 seconds
Started Aug 06 04:36:57 PM PDT 24
Finished Aug 06 04:37:00 PM PDT 24
Peak memory 205528 kb
Host smart-0346a064-03ab-48d0-8479-2087ef1a2342
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504100284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2504100284
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.924413426
Short name T446
Test name
Test status
Simulation time 195287721 ps
CPU time 1.1 seconds
Started Aug 06 04:37:02 PM PDT 24
Finished Aug 06 04:37:03 PM PDT 24
Peak memory 205244 kb
Host smart-69290bc8-98fa-4547-8169-2bd10468999e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924413426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.924413426
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.902041229
Short name T404
Test name
Test status
Simulation time 2554721248 ps
CPU time 4.82 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:36:59 PM PDT 24
Peak memory 205524 kb
Host smart-3a3cd298-44e0-43bb-81ca-770243b226e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902041229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.902041229
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3458615410
Short name T318
Test name
Test status
Simulation time 166357099 ps
CPU time 3.95 seconds
Started Aug 06 04:36:57 PM PDT 24
Finished Aug 06 04:37:01 PM PDT 24
Peak memory 213840 kb
Host smart-968805be-d144-462e-b525-f07782d4638d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458615410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3458615410
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3886320564
Short name T389
Test name
Test status
Simulation time 2492472826 ps
CPU time 10.5 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:37:05 PM PDT 24
Peak memory 213728 kb
Host smart-1eeb0240-a969-4400-89ca-a222521a5f30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886320564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
886320564
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2032713360
Short name T100
Test name
Test status
Simulation time 1541710150 ps
CPU time 65.03 seconds
Started Aug 06 04:36:18 PM PDT 24
Finished Aug 06 04:37:23 PM PDT 24
Peak memory 205476 kb
Host smart-a054a649-f020-4c49-90a1-76dfab4b7b53
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032713360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2032713360
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.471698883
Short name T360
Test name
Test status
Simulation time 20492367575 ps
CPU time 70.12 seconds
Started Aug 06 04:36:25 PM PDT 24
Finished Aug 06 04:37:35 PM PDT 24
Peak memory 213796 kb
Host smart-92c005de-06a3-41e7-8b02-977b1625780c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471698883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.471698883
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.341773203
Short name T430
Test name
Test status
Simulation time 479946443 ps
CPU time 2.4 seconds
Started Aug 06 04:36:38 PM PDT 24
Finished Aug 06 04:36:41 PM PDT 24
Peak memory 214692 kb
Host smart-14740ded-9ee9-4822-ac9f-3fc962f95b1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341773203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.341773203
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2652105044
Short name T463
Test name
Test status
Simulation time 182340397 ps
CPU time 4.96 seconds
Started Aug 06 04:36:23 PM PDT 24
Finished Aug 06 04:36:28 PM PDT 24
Peak memory 219172 kb
Host smart-a79d2e66-414e-4ae7-bb39-656f9acd905b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652105044 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2652105044
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.98327831
Short name T371
Test name
Test status
Simulation time 111750969 ps
CPU time 2.2 seconds
Started Aug 06 04:36:24 PM PDT 24
Finished Aug 06 04:36:26 PM PDT 24
Peak memory 213692 kb
Host smart-0ac7bd2a-10ca-44ff-865a-e711a2b60511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98327831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.98327831
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3209767530
Short name T307
Test name
Test status
Simulation time 13077824586 ps
CPU time 39.02 seconds
Started Aug 06 04:36:25 PM PDT 24
Finished Aug 06 04:37:04 PM PDT 24
Peak memory 205492 kb
Host smart-ca3e7b16-ee10-4a64-8a6a-4dfc74cd9cf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209767530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3209767530
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1212962064
Short name T395
Test name
Test status
Simulation time 5470721652 ps
CPU time 5.36 seconds
Started Aug 06 04:36:17 PM PDT 24
Finished Aug 06 04:36:22 PM PDT 24
Peak memory 205468 kb
Host smart-65ff3f2e-e72c-4899-a7d4-9f6f289ee4db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212962064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1212962064
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.971555003
Short name T93
Test name
Test status
Simulation time 3216657184 ps
CPU time 5.3 seconds
Started Aug 06 04:36:27 PM PDT 24
Finished Aug 06 04:36:32 PM PDT 24
Peak memory 205556 kb
Host smart-733dfd66-8070-4493-95f8-51cb1fad24d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971555003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.971555003
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1638265186
Short name T410
Test name
Test status
Simulation time 1185380297 ps
CPU time 2.5 seconds
Started Aug 06 04:36:27 PM PDT 24
Finished Aug 06 04:36:30 PM PDT 24
Peak memory 205356 kb
Host smart-942116d8-cdfe-490e-898b-87904cd98940
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638265186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
638265186
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.240833841
Short name T345
Test name
Test status
Simulation time 1165028213 ps
CPU time 3.83 seconds
Started Aug 06 04:36:40 PM PDT 24
Finished Aug 06 04:36:43 PM PDT 24
Peak memory 205296 kb
Host smart-e0703d29-e8ac-43cf-b180-1d641c19cccc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240833841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.240833841
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.14790605
Short name T356
Test name
Test status
Simulation time 12521067674 ps
CPU time 8.86 seconds
Started Aug 06 04:36:39 PM PDT 24
Finished Aug 06 04:36:48 PM PDT 24
Peak memory 205488 kb
Host smart-2ce835a8-1eaf-4763-8ac8-235caf7665f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14790605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_
bit_bash.14790605
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.954479648
Short name T411
Test name
Test status
Simulation time 787550290 ps
CPU time 1.07 seconds
Started Aug 06 04:36:52 PM PDT 24
Finished Aug 06 04:36:54 PM PDT 24
Peak memory 205228 kb
Host smart-6e24a488-e29f-4a1d-b2cb-ef2c582a1375
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954479648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.954479648
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1117672696
Short name T51
Test name
Test status
Simulation time 111271945 ps
CPU time 0.8 seconds
Started Aug 06 04:36:35 PM PDT 24
Finished Aug 06 04:36:36 PM PDT 24
Peak memory 205212 kb
Host smart-2e9813f8-d374-4793-a785-06878602468d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117672696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
117672696
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2186961515
Short name T414
Test name
Test status
Simulation time 68626108 ps
CPU time 0.72 seconds
Started Aug 06 04:36:48 PM PDT 24
Finished Aug 06 04:36:48 PM PDT 24
Peak memory 205228 kb
Host smart-01cca375-fcee-41fb-811b-ebdb94584af9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186961515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2186961515
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2932357327
Short name T443
Test name
Test status
Simulation time 103471865 ps
CPU time 0.71 seconds
Started Aug 06 04:36:20 PM PDT 24
Finished Aug 06 04:36:21 PM PDT 24
Peak memory 205204 kb
Host smart-07147dde-8ac7-4426-82b6-eb6f9d71d386
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932357327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2932357327
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3011096343
Short name T84
Test name
Test status
Simulation time 186681803 ps
CPU time 6.41 seconds
Started Aug 06 04:36:24 PM PDT 24
Finished Aug 06 04:36:31 PM PDT 24
Peak memory 205488 kb
Host smart-0bec5ee2-c101-4a64-989e-baa30d41d203
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011096343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3011096343
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.4175573169
Short name T362
Test name
Test status
Simulation time 22665407665 ps
CPU time 19.39 seconds
Started Aug 06 04:36:25 PM PDT 24
Finished Aug 06 04:36:45 PM PDT 24
Peak memory 222060 kb
Host smart-8ab3b26b-332f-463c-a0d3-bf9900d9a23c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175573169 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.4175573169
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3331275467
Short name T114
Test name
Test status
Simulation time 615389851 ps
CPU time 3.98 seconds
Started Aug 06 04:36:20 PM PDT 24
Finished Aug 06 04:36:24 PM PDT 24
Peak memory 213768 kb
Host smart-35b08c2f-feca-4cdf-88b6-f7ac028088a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331275467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3331275467
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3261088151
Short name T455
Test name
Test status
Simulation time 4809141539 ps
CPU time 19.96 seconds
Started Aug 06 04:36:24 PM PDT 24
Finished Aug 06 04:36:44 PM PDT 24
Peak memory 213876 kb
Host smart-ba89ba04-4984-4a46-baf8-9a93135bf102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261088151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3261088151
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3542761110
Short name T96
Test name
Test status
Simulation time 837348791 ps
CPU time 25.79 seconds
Started Aug 06 04:37:01 PM PDT 24
Finished Aug 06 04:37:27 PM PDT 24
Peak memory 214716 kb
Host smart-d1a3430a-7332-4d7f-b4d7-67527249cd05
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542761110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3542761110
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1825474237
Short name T378
Test name
Test status
Simulation time 60767953934 ps
CPU time 52.81 seconds
Started Aug 06 04:36:17 PM PDT 24
Finished Aug 06 04:37:10 PM PDT 24
Peak memory 213796 kb
Host smart-6ce88a32-a1dd-4b72-8a57-4bf6046668f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825474237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1825474237
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.589379054
Short name T104
Test name
Test status
Simulation time 433516905 ps
CPU time 2.56 seconds
Started Aug 06 04:36:22 PM PDT 24
Finished Aug 06 04:36:25 PM PDT 24
Peak memory 213668 kb
Host smart-da1365e8-525e-419a-b97c-531f3e5408df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589379054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.589379054
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3939770658
Short name T325
Test name
Test status
Simulation time 117979862 ps
CPU time 2.2 seconds
Started Aug 06 04:36:47 PM PDT 24
Finished Aug 06 04:36:49 PM PDT 24
Peak memory 215776 kb
Host smart-9b06dfa8-5529-45f7-82d7-8bdb4b7dccbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939770658 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3939770658
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2799295690
Short name T85
Test name
Test status
Simulation time 245841838 ps
CPU time 2.31 seconds
Started Aug 06 04:36:36 PM PDT 24
Finished Aug 06 04:36:39 PM PDT 24
Peak memory 213700 kb
Host smart-adc90719-7c86-4936-9150-c2ee901656ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799295690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2799295690
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2143379464
Short name T396
Test name
Test status
Simulation time 109007633207 ps
CPU time 94.75 seconds
Started Aug 06 04:36:44 PM PDT 24
Finished Aug 06 04:38:19 PM PDT 24
Peak memory 205412 kb
Host smart-674f7348-3352-4eda-bfd0-07e17ed426ef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143379464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2143379464
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4276311376
Short name T340
Test name
Test status
Simulation time 41192461 ps
CPU time 0.81 seconds
Started Aug 06 04:36:24 PM PDT 24
Finished Aug 06 04:36:25 PM PDT 24
Peak memory 205136 kb
Host smart-60f47625-0b41-441f-a657-f6efb393b913
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276311376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.4276311376
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.123519564
Short name T90
Test name
Test status
Simulation time 3291819657 ps
CPU time 5.15 seconds
Started Aug 06 04:37:00 PM PDT 24
Finished Aug 06 04:37:10 PM PDT 24
Peak memory 205532 kb
Host smart-f1390351-d2fc-4f34-acd4-07e918dafb6d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123519564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.123519564
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.363223062
Short name T358
Test name
Test status
Simulation time 2063496168 ps
CPU time 2.39 seconds
Started Aug 06 04:36:36 PM PDT 24
Finished Aug 06 04:36:38 PM PDT 24
Peak memory 205292 kb
Host smart-5db134cb-d521-4c35-bc89-7ac73da61387
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363223062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.363223062
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3928194801
Short name T334
Test name
Test status
Simulation time 1110824523 ps
CPU time 1.16 seconds
Started Aug 06 04:36:23 PM PDT 24
Finished Aug 06 04:36:24 PM PDT 24
Peak memory 205136 kb
Host smart-5f94f052-4f1d-4d09-80e7-cb1a15b041db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928194801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3928194801
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1648847679
Short name T328
Test name
Test status
Simulation time 3601377107 ps
CPU time 4.21 seconds
Started Aug 06 04:36:31 PM PDT 24
Finished Aug 06 04:36:35 PM PDT 24
Peak memory 205476 kb
Host smart-0c2c0fd9-86b0-4215-9692-9dbe58a12b3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648847679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1648847679
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2259112153
Short name T403
Test name
Test status
Simulation time 358226024 ps
CPU time 1.55 seconds
Started Aug 06 04:36:25 PM PDT 24
Finished Aug 06 04:36:26 PM PDT 24
Peak memory 205196 kb
Host smart-419d4143-7ef3-4551-8e09-7c7860e0717b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259112153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2259112153
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1745196293
Short name T369
Test name
Test status
Simulation time 128280198 ps
CPU time 0.87 seconds
Started Aug 06 04:36:25 PM PDT 24
Finished Aug 06 04:36:26 PM PDT 24
Peak memory 205176 kb
Host smart-a4c2ec74-f990-47e6-b77c-91a8c1fb7645
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745196293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
745196293
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.769726264
Short name T407
Test name
Test status
Simulation time 46173760 ps
CPU time 0.7 seconds
Started Aug 06 04:36:31 PM PDT 24
Finished Aug 06 04:36:32 PM PDT 24
Peak memory 205212 kb
Host smart-5ecd63d9-951f-45c0-9be0-2e05f8285abb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769726264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.769726264
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1500427737
Short name T427
Test name
Test status
Simulation time 123801768 ps
CPU time 0.98 seconds
Started Aug 06 04:36:24 PM PDT 24
Finished Aug 06 04:36:25 PM PDT 24
Peak memory 204604 kb
Host smart-59d53894-0773-44f7-94b6-f89aa0ff8aca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500427737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1500427737
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.861167799
Short name T99
Test name
Test status
Simulation time 794798863 ps
CPU time 4.09 seconds
Started Aug 06 04:36:43 PM PDT 24
Finished Aug 06 04:36:48 PM PDT 24
Peak memory 205480 kb
Host smart-46180a6f-05ba-4f78-99fe-bada593a7cc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861167799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.861167799
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4032119050
Short name T49
Test name
Test status
Simulation time 51739272189 ps
CPU time 66.93 seconds
Started Aug 06 04:36:47 PM PDT 24
Finished Aug 06 04:37:54 PM PDT 24
Peak memory 221472 kb
Host smart-64a6c865-e8a3-47b7-8f9c-ec20b16c45db
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032119050 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.4032119050
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2606549210
Short name T336
Test name
Test status
Simulation time 347365260 ps
CPU time 5.12 seconds
Started Aug 06 04:36:27 PM PDT 24
Finished Aug 06 04:36:32 PM PDT 24
Peak memory 213740 kb
Host smart-4278713b-4428-4990-a0a0-9754adfd299f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606549210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2606549210
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3097100070
Short name T154
Test name
Test status
Simulation time 1829023597 ps
CPU time 16.15 seconds
Started Aug 06 04:36:21 PM PDT 24
Finished Aug 06 04:36:37 PM PDT 24
Peak memory 213664 kb
Host smart-18d712ed-0913-4c2c-89ed-e094490cc7f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097100070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3097100070
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2149340333
Short name T438
Test name
Test status
Simulation time 7104320114 ps
CPU time 74.89 seconds
Started Aug 06 04:36:38 PM PDT 24
Finished Aug 06 04:37:53 PM PDT 24
Peak memory 213740 kb
Host smart-b9c8f28d-7453-4415-a291-3e5db20e503a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149340333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2149340333
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2317718944
Short name T377
Test name
Test status
Simulation time 30244397343 ps
CPU time 77.88 seconds
Started Aug 06 04:36:31 PM PDT 24
Finished Aug 06 04:37:49 PM PDT 24
Peak memory 213740 kb
Host smart-194a3fdf-dd8d-4649-b0db-77fe5c71150d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317718944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2317718944
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.210570065
Short name T431
Test name
Test status
Simulation time 118605623 ps
CPU time 1.79 seconds
Started Aug 06 04:36:21 PM PDT 24
Finished Aug 06 04:36:23 PM PDT 24
Peak memory 213680 kb
Host smart-8d22f144-79e1-44a3-818d-95bd95efd931
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210570065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.210570065
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1686169685
Short name T320
Test name
Test status
Simulation time 492624943 ps
CPU time 3.8 seconds
Started Aug 06 04:36:38 PM PDT 24
Finished Aug 06 04:36:42 PM PDT 24
Peak memory 219332 kb
Host smart-57596344-68c1-4b59-829c-2a2d65139749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686169685 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1686169685
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.363986034
Short name T419
Test name
Test status
Simulation time 1505680001 ps
CPU time 2.59 seconds
Started Aug 06 04:36:38 PM PDT 24
Finished Aug 06 04:36:41 PM PDT 24
Peak memory 213668 kb
Host smart-f424397b-b370-4311-a109-d67dc7e764d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363986034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.363986034
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2870918878
Short name T365
Test name
Test status
Simulation time 37680316622 ps
CPU time 56.12 seconds
Started Aug 06 04:36:19 PM PDT 24
Finished Aug 06 04:37:15 PM PDT 24
Peak memory 205504 kb
Host smart-2a01ca4d-ccea-43a8-972a-9ccacea04c0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870918878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2870918878
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4284160620
Short name T426
Test name
Test status
Simulation time 57525862820 ps
CPU time 52.8 seconds
Started Aug 06 04:36:21 PM PDT 24
Finished Aug 06 04:37:14 PM PDT 24
Peak memory 205496 kb
Host smart-7d157da5-8c47-44e4-829f-b9a93f8dc5ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284160620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.4284160620
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1973041925
Short name T91
Test name
Test status
Simulation time 3430118349 ps
CPU time 11.76 seconds
Started Aug 06 04:36:37 PM PDT 24
Finished Aug 06 04:36:49 PM PDT 24
Peak memory 205668 kb
Host smart-ea158b05-aa4f-42e6-a5fd-279321cbe92e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973041925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1973041925
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1619919826
Short name T376
Test name
Test status
Simulation time 973351619 ps
CPU time 2.23 seconds
Started Aug 06 04:36:42 PM PDT 24
Finished Aug 06 04:36:44 PM PDT 24
Peak memory 205412 kb
Host smart-7ec647f0-39a0-443b-a491-cd12108210b5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619919826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
619919826
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1268661391
Short name T393
Test name
Test status
Simulation time 201805086 ps
CPU time 0.74 seconds
Started Aug 06 04:36:39 PM PDT 24
Finished Aug 06 04:36:40 PM PDT 24
Peak memory 205088 kb
Host smart-cbc91a9b-7411-44d7-b0c7-47d77a86d796
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268661391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1268661391
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2421046546
Short name T339
Test name
Test status
Simulation time 19757725751 ps
CPU time 22.48 seconds
Started Aug 06 04:36:22 PM PDT 24
Finished Aug 06 04:36:45 PM PDT 24
Peak memory 205532 kb
Host smart-6065e683-47ac-46e6-a0ee-1d40b461c693
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421046546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2421046546
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.60445756
Short name T437
Test name
Test status
Simulation time 512803584 ps
CPU time 1.57 seconds
Started Aug 06 04:36:16 PM PDT 24
Finished Aug 06 04:36:18 PM PDT 24
Peak memory 205192 kb
Host smart-7c05e822-97ab-4d02-b8eb-586b5ecc34bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60445756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_
hw_reset.60445756
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2910704809
Short name T368
Test name
Test status
Simulation time 894079337 ps
CPU time 1.08 seconds
Started Aug 06 04:36:19 PM PDT 24
Finished Aug 06 04:36:20 PM PDT 24
Peak memory 205160 kb
Host smart-78613ba8-47a9-4981-8a70-f81d2696dac0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910704809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
910704809
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2344003323
Short name T445
Test name
Test status
Simulation time 54554066 ps
CPU time 0.67 seconds
Started Aug 06 04:36:21 PM PDT 24
Finished Aug 06 04:36:22 PM PDT 24
Peak memory 205264 kb
Host smart-89f57e11-f8af-472e-8824-b37f7dcc5086
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344003323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2344003323
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2959962839
Short name T357
Test name
Test status
Simulation time 47780691 ps
CPU time 0.75 seconds
Started Aug 06 04:36:44 PM PDT 24
Finished Aug 06 04:36:45 PM PDT 24
Peak memory 205144 kb
Host smart-6bd8d4c7-b308-4346-8091-09ffe2019903
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959962839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2959962839
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1173954580
Short name T408
Test name
Test status
Simulation time 2942518836 ps
CPU time 5.43 seconds
Started Aug 06 04:36:36 PM PDT 24
Finished Aug 06 04:36:41 PM PDT 24
Peak memory 205644 kb
Host smart-b79ee5cb-841c-4cca-a2e1-0463ddecafa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173954580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1173954580
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.320347076
Short name T162
Test name
Test status
Simulation time 47901063537 ps
CPU time 140.34 seconds
Started Aug 06 04:36:34 PM PDT 24
Finished Aug 06 04:38:54 PM PDT 24
Peak memory 223120 kb
Host smart-30b28442-9a3b-4776-91e6-ed50aa0346af
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320347076 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.320347076
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1354197236
Short name T386
Test name
Test status
Simulation time 1512278673 ps
CPU time 6 seconds
Started Aug 06 04:36:50 PM PDT 24
Finished Aug 06 04:36:56 PM PDT 24
Peak memory 213764 kb
Host smart-f26f1f34-2e1b-4cc6-9273-9c8077f2b090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354197236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1354197236
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.89608645
Short name T151
Test name
Test status
Simulation time 5067619931 ps
CPU time 22.35 seconds
Started Aug 06 04:36:21 PM PDT 24
Finished Aug 06 04:36:44 PM PDT 24
Peak memory 213804 kb
Host smart-08c86b2a-ac18-4c7d-bc7c-f184cdb71462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89608645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.89608645
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4239852321
Short name T316
Test name
Test status
Simulation time 104291676 ps
CPU time 2.48 seconds
Started Aug 06 04:36:42 PM PDT 24
Finished Aug 06 04:36:44 PM PDT 24
Peak memory 219116 kb
Host smart-60891f23-1869-4571-8c6a-64d1770ae49f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239852321 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4239852321
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2662638895
Short name T94
Test name
Test status
Simulation time 249282049 ps
CPU time 2.35 seconds
Started Aug 06 04:36:33 PM PDT 24
Finished Aug 06 04:36:36 PM PDT 24
Peak memory 213668 kb
Host smart-1d014365-8f42-4034-8c83-5c4aebcb1ed8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662638895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2662638895
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2797647032
Short name T434
Test name
Test status
Simulation time 4923417093 ps
CPU time 4.21 seconds
Started Aug 06 04:36:56 PM PDT 24
Finished Aug 06 04:37:00 PM PDT 24
Peak memory 205516 kb
Host smart-4c10da26-5f07-46d3-9b9a-51a26b0905e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797647032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2797647032
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2980772518
Short name T348
Test name
Test status
Simulation time 1560352518 ps
CPU time 4.96 seconds
Started Aug 06 04:36:25 PM PDT 24
Finished Aug 06 04:36:30 PM PDT 24
Peak memory 205416 kb
Host smart-9ede4bba-29e7-4646-9890-3ae41f9b7c9c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980772518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
980772518
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1852976886
Short name T394
Test name
Test status
Simulation time 403048464 ps
CPU time 1.78 seconds
Started Aug 06 04:37:01 PM PDT 24
Finished Aug 06 04:37:03 PM PDT 24
Peak memory 205192 kb
Host smart-fd27b9ec-cefc-4e57-92f6-849020e68be1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852976886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
852976886
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.251747153
Short name T423
Test name
Test status
Simulation time 413731597 ps
CPU time 3.9 seconds
Started Aug 06 04:36:32 PM PDT 24
Finished Aug 06 04:36:36 PM PDT 24
Peak memory 205536 kb
Host smart-84a00c66-1a71-4cdf-af3c-90deed89a95b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251747153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.251747153
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2639443946
Short name T415
Test name
Test status
Simulation time 28025750727 ps
CPU time 78.44 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:38:10 PM PDT 24
Peak memory 213808 kb
Host smart-294c6cc6-9add-4b9d-809f-bf404b8bd8ca
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639443946 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2639443946
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2825119495
Short name T335
Test name
Test status
Simulation time 389054851 ps
CPU time 5.77 seconds
Started Aug 06 04:36:46 PM PDT 24
Finished Aug 06 04:36:52 PM PDT 24
Peak memory 213704 kb
Host smart-a514dec8-6ae3-4698-abc1-999096de9cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825119495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2825119495
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4191349806
Short name T460
Test name
Test status
Simulation time 1693614979 ps
CPU time 9.16 seconds
Started Aug 06 04:36:35 PM PDT 24
Finished Aug 06 04:36:44 PM PDT 24
Peak memory 213696 kb
Host smart-d9dba652-6743-4cf2-9f12-f9ac744a0eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191349806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.4191349806
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2271427201
Short name T350
Test name
Test status
Simulation time 241340266 ps
CPU time 2.37 seconds
Started Aug 06 04:36:49 PM PDT 24
Finished Aug 06 04:36:52 PM PDT 24
Peak memory 221952 kb
Host smart-b456aafa-92dc-4966-accd-c9d8970b5247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271427201 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2271427201
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1420229175
Short name T102
Test name
Test status
Simulation time 140761983 ps
CPU time 1.6 seconds
Started Aug 06 04:36:45 PM PDT 24
Finished Aug 06 04:36:47 PM PDT 24
Peak memory 213584 kb
Host smart-97e99a0b-5e49-485a-bd4a-2a1043548b5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420229175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1420229175
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4282983563
Short name T459
Test name
Test status
Simulation time 4274577091 ps
CPU time 6.89 seconds
Started Aug 06 04:36:32 PM PDT 24
Finished Aug 06 04:36:39 PM PDT 24
Peak memory 205500 kb
Host smart-7f5c1f46-09db-4709-ba66-e0ddc59228e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282983563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.4282983563
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1749274924
Short name T383
Test name
Test status
Simulation time 2632668699 ps
CPU time 4.17 seconds
Started Aug 06 04:36:31 PM PDT 24
Finished Aug 06 04:36:36 PM PDT 24
Peak memory 205480 kb
Host smart-4d23c172-ef17-47d9-a85e-3a01d60df5ef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749274924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
749274924
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3323318393
Short name T400
Test name
Test status
Simulation time 397108534 ps
CPU time 1.63 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:36:56 PM PDT 24
Peak memory 204804 kb
Host smart-1983428c-4139-4663-98d0-d5bef5ec4df8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323318393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
323318393
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1212632750
Short name T83
Test name
Test status
Simulation time 636793592 ps
CPU time 8.02 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:37:02 PM PDT 24
Peak memory 205424 kb
Host smart-3ad42ccb-fabc-4856-85ae-d81aaee50f5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212632750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1212632750
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3487594923
Short name T327
Test name
Test status
Simulation time 17493334286 ps
CPU time 20.4 seconds
Started Aug 06 04:36:45 PM PDT 24
Finished Aug 06 04:37:06 PM PDT 24
Peak memory 221192 kb
Host smart-b3c7641c-4750-41ba-83b9-375c6c078ccb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487594923 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3487594923
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3836874525
Short name T412
Test name
Test status
Simulation time 196262863 ps
CPU time 2.43 seconds
Started Aug 06 04:36:47 PM PDT 24
Finished Aug 06 04:36:49 PM PDT 24
Peak memory 213752 kb
Host smart-e2867fb4-6abd-4034-8cbb-6dbce6b7e380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836874525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3836874525
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2192251014
Short name T152
Test name
Test status
Simulation time 9740211085 ps
CPU time 20 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:37:14 PM PDT 24
Peak memory 213536 kb
Host smart-ad5a81ab-4c40-4e5b-83f0-cc02b80f09d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192251014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2192251014
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2364507443
Short name T113
Test name
Test status
Simulation time 346499896 ps
CPU time 3.67 seconds
Started Aug 06 04:36:55 PM PDT 24
Finished Aug 06 04:36:59 PM PDT 24
Peak memory 221932 kb
Host smart-946e3bc5-67b7-47a3-9b68-40c23335eb65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364507443 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2364507443
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2523294313
Short name T347
Test name
Test status
Simulation time 63031557440 ps
CPU time 42 seconds
Started Aug 06 04:36:43 PM PDT 24
Finished Aug 06 04:37:25 PM PDT 24
Peak memory 205408 kb
Host smart-a4fe9105-0a6b-418e-9eeb-6b863766fc70
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523294313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2523294313
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.574530566
Short name T421
Test name
Test status
Simulation time 3389616109 ps
CPU time 5.32 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:36:56 PM PDT 24
Peak memory 205464 kb
Host smart-d310593c-f03d-45d2-b83a-87ab8f7b8b6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574530566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.574530566
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1997281325
Short name T359
Test name
Test status
Simulation time 186698379 ps
CPU time 0.88 seconds
Started Aug 06 04:36:52 PM PDT 24
Finished Aug 06 04:36:53 PM PDT 24
Peak memory 205208 kb
Host smart-024250a2-74e0-45c1-8c80-27142bc06121
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997281325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
997281325
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.388323656
Short name T462
Test name
Test status
Simulation time 269724777 ps
CPU time 4.13 seconds
Started Aug 06 04:36:56 PM PDT 24
Finished Aug 06 04:37:00 PM PDT 24
Peak memory 205512 kb
Host smart-172e35b6-b2b3-4481-8d9c-bb30cc3a2141
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388323656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.388323656
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.470074697
Short name T447
Test name
Test status
Simulation time 22641167501 ps
CPU time 62.04 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:37:56 PM PDT 24
Peak memory 222152 kb
Host smart-e2f5d279-4fbe-48de-9163-48c01c9e2c1d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470074697 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.470074697
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1157962159
Short name T333
Test name
Test status
Simulation time 307664600 ps
CPU time 4.94 seconds
Started Aug 06 04:36:37 PM PDT 24
Finished Aug 06 04:36:42 PM PDT 24
Peak memory 213764 kb
Host smart-a2cc1100-a022-44ed-a580-38e02e487429
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157962159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1157962159
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2403309321
Short name T157
Test name
Test status
Simulation time 1564990777 ps
CPU time 9.58 seconds
Started Aug 06 04:36:54 PM PDT 24
Finished Aug 06 04:37:04 PM PDT 24
Peak memory 213744 kb
Host smart-f0d23b4b-1e71-4596-85ad-ddb7ac0fcdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403309321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2403309321
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1208488068
Short name T424
Test name
Test status
Simulation time 363426222 ps
CPU time 2.57 seconds
Started Aug 06 04:36:57 PM PDT 24
Finished Aug 06 04:37:00 PM PDT 24
Peak memory 217240 kb
Host smart-22fbd398-b387-489f-a74b-ec62cc6ea89c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208488068 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1208488068
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1743431516
Short name T456
Test name
Test status
Simulation time 75497529 ps
CPU time 1.48 seconds
Started Aug 06 04:36:33 PM PDT 24
Finished Aug 06 04:36:34 PM PDT 24
Peak memory 213620 kb
Host smart-247d616a-05f3-4157-b887-7c5ecc49a0eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743431516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1743431516
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4078569670
Short name T324
Test name
Test status
Simulation time 54791005687 ps
CPU time 81.64 seconds
Started Aug 06 04:36:30 PM PDT 24
Finished Aug 06 04:37:52 PM PDT 24
Peak memory 205448 kb
Host smart-fb11a328-8b7e-4dbc-9912-8f06630817fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078569670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.4078569670
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.822873775
Short name T436
Test name
Test status
Simulation time 2632197567 ps
CPU time 4.49 seconds
Started Aug 06 04:36:43 PM PDT 24
Finished Aug 06 04:36:48 PM PDT 24
Peak memory 205512 kb
Host smart-87c16b6d-0f4f-4c60-bb68-96f7ba406301
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822873775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.822873775
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.905563618
Short name T379
Test name
Test status
Simulation time 1010352050 ps
CPU time 3.63 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:36:55 PM PDT 24
Peak memory 205148 kb
Host smart-8ad9681e-46c4-4b37-9a79-885879bd87a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905563618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.905563618
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2887783904
Short name T110
Test name
Test status
Simulation time 197470144 ps
CPU time 6.73 seconds
Started Aug 06 04:36:33 PM PDT 24
Finished Aug 06 04:36:40 PM PDT 24
Peak memory 205896 kb
Host smart-35ad9207-62c3-445a-a4e1-54b8e763b962
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887783904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2887783904
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3878307335
Short name T416
Test name
Test status
Simulation time 13983835211 ps
CPU time 15.85 seconds
Started Aug 06 04:36:35 PM PDT 24
Finished Aug 06 04:36:51 PM PDT 24
Peak memory 218660 kb
Host smart-e38dad10-9a0a-4e5f-a754-e1ea4c0c8b39
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878307335 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3878307335
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2310648054
Short name T402
Test name
Test status
Simulation time 513952455 ps
CPU time 5.29 seconds
Started Aug 06 04:36:35 PM PDT 24
Finished Aug 06 04:36:41 PM PDT 24
Peak memory 213800 kb
Host smart-0eba7d19-8415-4508-a313-c4b0791067a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310648054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2310648054
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2575872105
Short name T153
Test name
Test status
Simulation time 10586242668 ps
CPU time 24.21 seconds
Started Aug 06 04:36:34 PM PDT 24
Finished Aug 06 04:36:59 PM PDT 24
Peak memory 214480 kb
Host smart-69b01bba-025f-4445-9c64-03a94a0f6950
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575872105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2575872105
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3183144681
Short name T366
Test name
Test status
Simulation time 268444357 ps
CPU time 4.11 seconds
Started Aug 06 04:36:37 PM PDT 24
Finished Aug 06 04:36:41 PM PDT 24
Peak memory 221244 kb
Host smart-2aafb448-fc04-4d27-82fc-0a7d29c319c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183144681 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3183144681
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3224581891
Short name T374
Test name
Test status
Simulation time 295207908 ps
CPU time 2.39 seconds
Started Aug 06 04:36:37 PM PDT 24
Finished Aug 06 04:36:40 PM PDT 24
Peak memory 213380 kb
Host smart-1dc1a059-4677-4b64-92c8-4cc8f16b4d9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224581891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3224581891
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3230580100
Short name T305
Test name
Test status
Simulation time 33418124471 ps
CPU time 70.27 seconds
Started Aug 06 04:36:34 PM PDT 24
Finished Aug 06 04:37:44 PM PDT 24
Peak memory 205408 kb
Host smart-4926b254-a144-41e5-a0d3-ef761f90911d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230580100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3230580100
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3909483347
Short name T453
Test name
Test status
Simulation time 6769687943 ps
CPU time 10.03 seconds
Started Aug 06 04:36:34 PM PDT 24
Finished Aug 06 04:36:44 PM PDT 24
Peak memory 205424 kb
Host smart-5e18f23a-78ee-4847-a06b-39126e9109ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909483347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
909483347
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3066357985
Short name T448
Test name
Test status
Simulation time 450042424 ps
CPU time 1.05 seconds
Started Aug 06 04:36:51 PM PDT 24
Finished Aug 06 04:36:52 PM PDT 24
Peak memory 205124 kb
Host smart-a8379a26-5b0a-4fca-bab0-829a7a7d572f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066357985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
066357985
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.279944150
Short name T80
Test name
Test status
Simulation time 449246865 ps
CPU time 7.66 seconds
Started Aug 06 04:36:45 PM PDT 24
Finished Aug 06 04:36:53 PM PDT 24
Peak memory 205540 kb
Host smart-da7a5f5b-ed9f-4705-ac5a-191a78e0ced5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279944150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.279944150
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1342730646
Short name T372
Test name
Test status
Simulation time 13806471173 ps
CPU time 103.69 seconds
Started Aug 06 04:36:35 PM PDT 24
Finished Aug 06 04:38:19 PM PDT 24
Peak memory 220432 kb
Host smart-4165c2a8-5661-4ef7-9338-a7c82d672ca9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342730646 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1342730646
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2780591419
Short name T319
Test name
Test status
Simulation time 839946667 ps
CPU time 4.66 seconds
Started Aug 06 04:36:37 PM PDT 24
Finished Aug 06 04:36:42 PM PDT 24
Peak memory 213760 kb
Host smart-937065f2-b300-496c-b98f-3629cd341e94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780591419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2780591419
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1699816678
Short name T155
Test name
Test status
Simulation time 3016152983 ps
CPU time 10.22 seconds
Started Aug 06 04:36:36 PM PDT 24
Finished Aug 06 04:36:47 PM PDT 24
Peak memory 213836 kb
Host smart-3ac0e4c4-d070-4cd1-a6fd-56cede3b7964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699816678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1699816678
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2594984648
Short name T18
Test name
Test status
Simulation time 1306188320 ps
CPU time 1.6 seconds
Started Aug 06 04:42:58 PM PDT 24
Finished Aug 06 04:43:00 PM PDT 24
Peak memory 204468 kb
Host smart-95522d14-dc9e-4ae6-ae27-668e72abdf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594984648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2594984648
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1463059578
Short name T255
Test name
Test status
Simulation time 843174559 ps
CPU time 1.75 seconds
Started Aug 06 04:43:01 PM PDT 24
Finished Aug 06 04:43:03 PM PDT 24
Peak memory 205124 kb
Host smart-b78da625-fe15-4dd5-a735-0a82623544a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463059578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1463059578
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2370954097
Short name T147
Test name
Test status
Simulation time 126094512 ps
CPU time 0.74 seconds
Started Aug 06 04:43:00 PM PDT 24
Finished Aug 06 04:43:01 PM PDT 24
Peak memory 205136 kb
Host smart-04651f22-4ddb-4586-8375-e19fd3bb47fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370954097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2370954097
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2353166561
Short name T56
Test name
Test status
Simulation time 123313183 ps
CPU time 1.13 seconds
Started Aug 06 04:43:10 PM PDT 24
Finished Aug 06 04:43:11 PM PDT 24
Peak memory 215484 kb
Host smart-c4191a7d-7837-40ad-abe5-13de1eab01cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353166561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2353166561
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1346620384
Short name T252
Test name
Test status
Simulation time 5014874730 ps
CPU time 15.09 seconds
Started Aug 06 04:42:51 PM PDT 24
Finished Aug 06 04:43:06 PM PDT 24
Peak memory 213804 kb
Host smart-832bf8e7-4f04-4562-b9a7-b007921f9b53
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346620384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1346620384
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2782088225
Short name T237
Test name
Test status
Simulation time 717635512 ps
CPU time 1.01 seconds
Started Aug 06 04:42:55 PM PDT 24
Finished Aug 06 04:42:56 PM PDT 24
Peak memory 205120 kb
Host smart-2f0e2d04-171c-40ad-8c11-21f3e796b28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782088225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2782088225
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1261549448
Short name T121
Test name
Test status
Simulation time 364666459 ps
CPU time 1.2 seconds
Started Aug 06 04:42:52 PM PDT 24
Finished Aug 06 04:42:54 PM PDT 24
Peak memory 204972 kb
Host smart-2df197b5-edc0-437b-b1d5-f0e882810cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261549448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1261549448
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4177203676
Short name T268
Test name
Test status
Simulation time 155912489 ps
CPU time 1.08 seconds
Started Aug 06 04:42:53 PM PDT 24
Finished Aug 06 04:42:54 PM PDT 24
Peak memory 205132 kb
Host smart-518442a3-c642-43ba-8224-8732cd90769e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177203676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4177203676
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2037267909
Short name T178
Test name
Test status
Simulation time 1464891751 ps
CPU time 4.08 seconds
Started Aug 06 04:42:52 PM PDT 24
Finished Aug 06 04:42:56 PM PDT 24
Peak memory 205004 kb
Host smart-0fb8bc41-840d-4734-a877-577376137300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037267909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2037267909
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.420049454
Short name T270
Test name
Test status
Simulation time 158984045 ps
CPU time 1.15 seconds
Started Aug 06 04:43:00 PM PDT 24
Finished Aug 06 04:43:01 PM PDT 24
Peak memory 205140 kb
Host smart-4be43c55-013e-4b0a-8388-3767963f579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420049454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.420049454
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4119894714
Short name T272
Test name
Test status
Simulation time 242104821 ps
CPU time 1.3 seconds
Started Aug 06 04:43:12 PM PDT 24
Finished Aug 06 04:43:14 PM PDT 24
Peak memory 205196 kb
Host smart-ecdc5000-447f-452f-863b-0411a3001a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119894714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.4119894714
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1429719565
Short name T275
Test name
Test status
Simulation time 574545410 ps
CPU time 0.91 seconds
Started Aug 06 04:42:54 PM PDT 24
Finished Aug 06 04:42:55 PM PDT 24
Peak memory 204972 kb
Host smart-60a7d766-71c8-4d99-bd23-b28c7fa35ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429719565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1429719565
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.543402349
Short name T292
Test name
Test status
Simulation time 3168040175 ps
CPU time 2.79 seconds
Started Aug 06 04:42:54 PM PDT 24
Finished Aug 06 04:42:57 PM PDT 24
Peak memory 205096 kb
Host smart-13cf0d16-a416-4e36-93a8-36ab16613f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543402349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.543402349
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.693936633
Short name T163
Test name
Test status
Simulation time 463619314 ps
CPU time 1.82 seconds
Started Aug 06 04:43:12 PM PDT 24
Finished Aug 06 04:43:14 PM PDT 24
Peak memory 213404 kb
Host smart-6fb217e2-ac73-424b-81d3-75cf11ca86dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693936633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.693936633
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2671315661
Short name T37
Test name
Test status
Simulation time 206239876 ps
CPU time 0.82 seconds
Started Aug 06 04:43:10 PM PDT 24
Finished Aug 06 04:43:11 PM PDT 24
Peak memory 205148 kb
Host smart-ede04e28-1d33-40e8-a12e-99f148c6e35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671315661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2671315661
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1427366849
Short name T165
Test name
Test status
Simulation time 3047600669 ps
CPU time 8.64 seconds
Started Aug 06 04:43:07 PM PDT 24
Finished Aug 06 04:43:16 PM PDT 24
Peak memory 213816 kb
Host smart-56abe8bf-c07a-489f-a597-4765ac227c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427366849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1427366849
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1559240613
Short name T44
Test name
Test status
Simulation time 1074445320 ps
CPU time 4.04 seconds
Started Aug 06 04:43:17 PM PDT 24
Finished Aug 06 04:43:21 PM PDT 24
Peak memory 228828 kb
Host smart-5c3a7013-acd4-4bad-8b96-0797098ed0a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559240613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1559240613
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.336909815
Short name T205
Test name
Test status
Simulation time 1237135422 ps
CPU time 1.05 seconds
Started Aug 06 04:42:59 PM PDT 24
Finished Aug 06 04:43:00 PM PDT 24
Peak memory 205124 kb
Host smart-55c3b18e-1973-41d1-a18b-554a339a6551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336909815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.336909815
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.2732065092
Short name T10
Test name
Test status
Simulation time 123400541705 ps
CPU time 703.87 seconds
Started Aug 06 04:42:57 PM PDT 24
Finished Aug 06 04:54:41 PM PDT 24
Peak memory 238360 kb
Host smart-96d7a0e2-e559-488b-b6f0-c6b2d79f280d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732065092 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.2732065092
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1501976660
Short name T38
Test name
Test status
Simulation time 574887524 ps
CPU time 2.07 seconds
Started Aug 06 04:43:06 PM PDT 24
Finished Aug 06 04:43:09 PM PDT 24
Peak memory 205120 kb
Host smart-a34e9ca2-5a33-468c-bf3e-fd344d76882b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501976660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1501976660
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2618233551
Short name T194
Test name
Test status
Simulation time 139867034 ps
CPU time 0.77 seconds
Started Aug 06 04:43:15 PM PDT 24
Finished Aug 06 04:43:15 PM PDT 24
Peak memory 205188 kb
Host smart-4f0ac9f5-b9d8-4c62-9e6c-e24b58c94d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618233551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2618233551
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2696923895
Short name T129
Test name
Test status
Simulation time 10291545663 ps
CPU time 32.18 seconds
Started Aug 06 04:43:14 PM PDT 24
Finished Aug 06 04:43:46 PM PDT 24
Peak memory 213804 kb
Host smart-ac5b0ffc-4fc3-4029-a1ea-51d53ab8c0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696923895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2696923895
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2053724461
Short name T11
Test name
Test status
Simulation time 4711275801 ps
CPU time 13.14 seconds
Started Aug 06 04:43:06 PM PDT 24
Finished Aug 06 04:43:20 PM PDT 24
Peak memory 213884 kb
Host smart-31ebc97e-4a2a-48e2-b4a6-e6ec66079dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053724461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2053724461
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2734938340
Short name T257
Test name
Test status
Simulation time 1147129752 ps
CPU time 1.46 seconds
Started Aug 06 04:43:04 PM PDT 24
Finished Aug 06 04:43:05 PM PDT 24
Peak memory 205140 kb
Host smart-6f231fdf-7f80-464f-9877-0dafdb26247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734938340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2734938340
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1813372018
Short name T15
Test name
Test status
Simulation time 859867376 ps
CPU time 1.1 seconds
Started Aug 06 04:43:00 PM PDT 24
Finished Aug 06 04:43:01 PM PDT 24
Peak memory 205160 kb
Host smart-01b7d49b-bcae-4323-91d6-1df7fe9f133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813372018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1813372018
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.4151123731
Short name T26
Test name
Test status
Simulation time 1359687586 ps
CPU time 4.42 seconds
Started Aug 06 04:42:55 PM PDT 24
Finished Aug 06 04:43:00 PM PDT 24
Peak memory 205156 kb
Host smart-4bffa16c-166f-43d8-aae1-40e0e2d42a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151123731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.4151123731
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.4281916313
Short name T259
Test name
Test status
Simulation time 196881826 ps
CPU time 1.13 seconds
Started Aug 06 04:43:06 PM PDT 24
Finished Aug 06 04:43:08 PM PDT 24
Peak memory 205180 kb
Host smart-bcc05fbb-b52f-4573-8c2e-2e6713d25033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281916313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.4281916313
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.250199252
Short name T217
Test name
Test status
Simulation time 96409426 ps
CPU time 0.88 seconds
Started Aug 06 04:43:06 PM PDT 24
Finished Aug 06 04:43:07 PM PDT 24
Peak memory 205180 kb
Host smart-cd370286-00c6-4127-a71f-e793b95f26f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250199252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.250199252
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2651739149
Short name T261
Test name
Test status
Simulation time 60802602 ps
CPU time 0.92 seconds
Started Aug 06 04:43:03 PM PDT 24
Finished Aug 06 04:43:04 PM PDT 24
Peak memory 215288 kb
Host smart-d09e7946-d13c-4842-b0b9-67004f45922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651739149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2651739149
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2947042331
Short name T287
Test name
Test status
Simulation time 5872189857 ps
CPU time 9.08 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:20 PM PDT 24
Peak memory 205608 kb
Host smart-37444618-c47a-4082-a984-030618c85a8f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2947042331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2947042331
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.309562983
Short name T45
Test name
Test status
Simulation time 197476238 ps
CPU time 0.81 seconds
Started Aug 06 04:43:14 PM PDT 24
Finished Aug 06 04:43:15 PM PDT 24
Peak memory 205180 kb
Host smart-ed73240c-af50-466b-b1b1-68e58d77d7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309562983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.309562983
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3149568577
Short name T225
Test name
Test status
Simulation time 247450240 ps
CPU time 1.39 seconds
Started Aug 06 04:43:05 PM PDT 24
Finished Aug 06 04:43:07 PM PDT 24
Peak memory 205120 kb
Host smart-7d1b74d0-6edc-4664-95c9-28a4d044597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149568577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3149568577
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1537086383
Short name T300
Test name
Test status
Simulation time 179494609 ps
CPU time 0.98 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:12 PM PDT 24
Peak memory 205156 kb
Host smart-169e9a45-8646-4516-a820-a344ee18d69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537086383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1537086383
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.484095015
Short name T189
Test name
Test status
Simulation time 155052631 ps
CPU time 1.12 seconds
Started Aug 06 04:43:01 PM PDT 24
Finished Aug 06 04:43:03 PM PDT 24
Peak memory 204896 kb
Host smart-c10b703d-3989-4079-bab6-296d994dfdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484095015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.484095015
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1692508505
Short name T123
Test name
Test status
Simulation time 284593379 ps
CPU time 1.47 seconds
Started Aug 06 04:43:03 PM PDT 24
Finished Aug 06 04:43:05 PM PDT 24
Peak memory 205024 kb
Host smart-ae9a6137-11d1-41af-b932-d0b43bfa377e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692508505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1692508505
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.4074722607
Short name T187
Test name
Test status
Simulation time 167465879 ps
CPU time 1.22 seconds
Started Aug 06 04:43:01 PM PDT 24
Finished Aug 06 04:43:03 PM PDT 24
Peak memory 204888 kb
Host smart-c913d1b3-4f8e-4cf3-8b2a-38026efeda32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074722607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.4074722607
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.548302761
Short name T251
Test name
Test status
Simulation time 209326625 ps
CPU time 1.25 seconds
Started Aug 06 04:43:06 PM PDT 24
Finished Aug 06 04:43:07 PM PDT 24
Peak memory 205196 kb
Host smart-1839e2ab-e41b-4f8d-be9b-cf4096fe4d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548302761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.548302761
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2459456557
Short name T224
Test name
Test status
Simulation time 111575570 ps
CPU time 0.84 seconds
Started Aug 06 04:43:00 PM PDT 24
Finished Aug 06 04:43:01 PM PDT 24
Peak memory 205140 kb
Host smart-1680d9f6-fcad-4cf3-bc7f-35c82fd38e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459456557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2459456557
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2981054283
Short name T223
Test name
Test status
Simulation time 267201026 ps
CPU time 0.97 seconds
Started Aug 06 04:43:07 PM PDT 24
Finished Aug 06 04:43:13 PM PDT 24
Peak memory 205160 kb
Host smart-d92af7de-af4a-47c0-8dfc-efe33c02a4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981054283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2981054283
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.843509448
Short name T216
Test name
Test status
Simulation time 109338194 ps
CPU time 1.01 seconds
Started Aug 06 04:42:53 PM PDT 24
Finished Aug 06 04:42:54 PM PDT 24
Peak memory 213328 kb
Host smart-713f684e-d0b5-417d-b5db-60c13dbffab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843509448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.843509448
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1903697323
Short name T62
Test name
Test status
Simulation time 782057196 ps
CPU time 1.34 seconds
Started Aug 06 04:43:01 PM PDT 24
Finished Aug 06 04:43:02 PM PDT 24
Peak memory 205128 kb
Host smart-31b3581c-b34c-407e-9fa8-5f95724e564b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903697323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1903697323
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.100141143
Short name T29
Test name
Test status
Simulation time 38540758 ps
CPU time 0.83 seconds
Started Aug 06 04:43:05 PM PDT 24
Finished Aug 06 04:43:06 PM PDT 24
Peak memory 213348 kb
Host smart-7401de59-e7a8-46db-b7e6-a4390efc0a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100141143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.100141143
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2260050066
Short name T122
Test name
Test status
Simulation time 2406059170 ps
CPU time 3.98 seconds
Started Aug 06 04:43:08 PM PDT 24
Finished Aug 06 04:43:12 PM PDT 24
Peak memory 205404 kb
Host smart-e95063df-6452-409a-aa70-5119c0addbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260050066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2260050066
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3894911725
Short name T248
Test name
Test status
Simulation time 790588740 ps
CPU time 1.94 seconds
Started Aug 06 04:43:01 PM PDT 24
Finished Aug 06 04:43:03 PM PDT 24
Peak memory 205584 kb
Host smart-9895e26f-a1f8-47ef-b6ad-5fe5d1f8c668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894911725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3894911725
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.83330072
Short name T57
Test name
Test status
Simulation time 2528982399 ps
CPU time 2.65 seconds
Started Aug 06 04:43:09 PM PDT 24
Finished Aug 06 04:43:12 PM PDT 24
Peak memory 229452 kb
Host smart-349a9a8f-c99d-4bdf-a263-2b81364a325e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83330072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.83330072
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3414957948
Short name T239
Test name
Test status
Simulation time 671180001 ps
CPU time 1.88 seconds
Started Aug 06 04:42:52 PM PDT 24
Finished Aug 06 04:42:54 PM PDT 24
Peak memory 205120 kb
Host smart-3143dedf-0578-4cce-a27e-26487a456747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414957948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3414957948
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1814653165
Short name T297
Test name
Test status
Simulation time 701101814 ps
CPU time 1.64 seconds
Started Aug 06 04:43:12 PM PDT 24
Finished Aug 06 04:43:13 PM PDT 24
Peak memory 205304 kb
Host smart-3afe92e1-43a7-472e-9bb5-1f90a9c4dfd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814653165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1814653165
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.373596795
Short name T73
Test name
Test status
Simulation time 356739704816 ps
CPU time 1200.27 seconds
Started Aug 06 04:43:20 PM PDT 24
Finished Aug 06 05:03:20 PM PDT 24
Peak memory 238704 kb
Host smart-2f390138-3980-4875-a978-f6330d12783b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373596795 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.373596795
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3211617016
Short name T254
Test name
Test status
Simulation time 66111754 ps
CPU time 0.73 seconds
Started Aug 06 04:43:18 PM PDT 24
Finished Aug 06 04:43:19 PM PDT 24
Peak memory 205184 kb
Host smart-257981a0-223d-412e-b7c5-37a016a3f8f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211617016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3211617016
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2660453900
Short name T181
Test name
Test status
Simulation time 24316818261 ps
CPU time 24.93 seconds
Started Aug 06 04:43:15 PM PDT 24
Finished Aug 06 04:43:40 PM PDT 24
Peak memory 205632 kb
Host smart-285af20a-8bab-4bb5-bd4c-6ce1f37e098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660453900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2660453900
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.734015662
Short name T190
Test name
Test status
Simulation time 5366341673 ps
CPU time 14.21 seconds
Started Aug 06 04:43:22 PM PDT 24
Finished Aug 06 04:43:37 PM PDT 24
Peak memory 205704 kb
Host smart-e922f52b-ca17-42d0-a458-8771a1706f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734015662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.734015662
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3780126515
Short name T249
Test name
Test status
Simulation time 10223491194 ps
CPU time 5.19 seconds
Started Aug 06 04:43:19 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 213828 kb
Host smart-afb0b5f4-e648-4207-8a5b-9dcc296882e7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3780126515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3780126515
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.156993155
Short name T202
Test name
Test status
Simulation time 5099543201 ps
CPU time 14.94 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:47 PM PDT 24
Peak memory 205716 kb
Host smart-ee114650-c926-4a4e-b525-08675dc963c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156993155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.156993155
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.280643782
Short name T212
Test name
Test status
Simulation time 75620739 ps
CPU time 0.75 seconds
Started Aug 06 04:43:27 PM PDT 24
Finished Aug 06 04:43:28 PM PDT 24
Peak memory 205108 kb
Host smart-451f5d20-372b-4afe-ac06-e085c24310d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280643782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.280643782
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.17365384
Short name T166
Test name
Test status
Simulation time 29198521981 ps
CPU time 27.17 seconds
Started Aug 06 04:43:21 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 213756 kb
Host smart-6d6ad9d5-77f2-4e48-a4a7-d9de5e2ebd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17365384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.17365384
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3640779910
Short name T71
Test name
Test status
Simulation time 1807009388 ps
CPU time 4.18 seconds
Started Aug 06 04:43:27 PM PDT 24
Finished Aug 06 04:43:31 PM PDT 24
Peak memory 213628 kb
Host smart-f8880455-8abb-4ad4-9216-a5931dd83e5f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640779910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3640779910
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.609708105
Short name T179
Test name
Test status
Simulation time 7791723039 ps
CPU time 8.66 seconds
Started Aug 06 04:43:25 PM PDT 24
Finished Aug 06 04:43:33 PM PDT 24
Peak memory 213828 kb
Host smart-9530887d-4bc0-4973-abe6-64c6344b3abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609708105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.609708105
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.1219740867
Short name T118
Test name
Test status
Simulation time 5433038386 ps
CPU time 4.9 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:37 PM PDT 24
Peak memory 213640 kb
Host smart-5259a17f-72a7-46e1-861c-25bd89d95d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219740867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1219740867
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.46396235
Short name T55
Test name
Test status
Simulation time 114848975 ps
CPU time 0.74 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:33 PM PDT 24
Peak memory 205156 kb
Host smart-99d7a43f-6ee5-4f72-a15e-0f8be2c0ba0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46396235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.46396235
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1557321627
Short name T267
Test name
Test status
Simulation time 1181457040 ps
CPU time 1.9 seconds
Started Aug 06 04:43:16 PM PDT 24
Finished Aug 06 04:43:18 PM PDT 24
Peak memory 205512 kb
Host smart-47ed8547-d934-47c4-b3ee-b2ed33df340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557321627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1557321627
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2500916247
Short name T236
Test name
Test status
Simulation time 2422246310 ps
CPU time 5.04 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 205684 kb
Host smart-64ed2e78-f0f8-4a0b-af84-e36e2b2a7e48
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500916247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2500916247
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2226665480
Short name T244
Test name
Test status
Simulation time 2418269341 ps
CPU time 7.11 seconds
Started Aug 06 04:43:26 PM PDT 24
Finished Aug 06 04:43:33 PM PDT 24
Peak memory 205624 kb
Host smart-108368ef-a6dc-4cc9-9e5e-992b21496a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226665480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2226665480
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2524985836
Short name T246
Test name
Test status
Simulation time 2091907522 ps
CPU time 6.48 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:18 PM PDT 24
Peak memory 213528 kb
Host smart-9a109e97-a7b6-497d-ac91-a3658bc83b33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524985836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2524985836
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2801518172
Short name T201
Test name
Test status
Simulation time 34341825 ps
CPU time 0.74 seconds
Started Aug 06 04:43:24 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 205244 kb
Host smart-43f1d1c0-a0b3-44c9-8cd3-e372483bb2aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801518172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2801518172
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2779675287
Short name T260
Test name
Test status
Simulation time 7781340058 ps
CPU time 17.08 seconds
Started Aug 06 04:43:15 PM PDT 24
Finished Aug 06 04:43:32 PM PDT 24
Peak memory 213816 kb
Host smart-93d80b21-30c4-4285-992b-7ec1c3886470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779675287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2779675287
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2876099361
Short name T124
Test name
Test status
Simulation time 2313040913 ps
CPU time 4.79 seconds
Started Aug 06 04:43:31 PM PDT 24
Finished Aug 06 04:43:36 PM PDT 24
Peak memory 213840 kb
Host smart-6e17561f-16ac-472a-b251-fd9bd348a8e1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876099361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2876099361
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1651726471
Short name T63
Test name
Test status
Simulation time 4316597107 ps
CPU time 4.31 seconds
Started Aug 06 04:43:28 PM PDT 24
Finished Aug 06 04:43:32 PM PDT 24
Peak memory 213876 kb
Host smart-43c7d1b4-a8c8-4e4b-a349-97700eda35ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651726471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1651726471
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.882502788
Short name T127
Test name
Test status
Simulation time 5121303079 ps
CPU time 5.45 seconds
Started Aug 06 04:43:26 PM PDT 24
Finished Aug 06 04:43:31 PM PDT 24
Peak memory 213628 kb
Host smart-92789012-97fe-432d-b765-c67f279cc091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882502788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.882502788
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.4225861283
Short name T208
Test name
Test status
Simulation time 63210949 ps
CPU time 0.72 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:33 PM PDT 24
Peak memory 205160 kb
Host smart-3292f32e-098a-4567-8a28-5a5ff449bdda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225861283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.4225861283
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.4176255811
Short name T282
Test name
Test status
Simulation time 8009530922 ps
CPU time 4.5 seconds
Started Aug 06 04:43:20 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 213704 kb
Host smart-39bd6478-20c4-4e7e-9523-0d1e3726a5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176255811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.4176255811
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1112210575
Short name T280
Test name
Test status
Simulation time 2507091649 ps
CPU time 2.07 seconds
Started Aug 06 04:43:14 PM PDT 24
Finished Aug 06 04:43:16 PM PDT 24
Peak memory 213852 kb
Host smart-ba2fc8a8-6bbe-48ea-87d3-4ed87e2a1647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112210575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1112210575
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1519023232
Short name T204
Test name
Test status
Simulation time 10362390001 ps
CPU time 16.3 seconds
Started Aug 06 04:43:25 PM PDT 24
Finished Aug 06 04:43:41 PM PDT 24
Peak memory 213760 kb
Host smart-e348a9d6-c79b-4e2b-a463-494efef3f906
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1519023232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1519023232
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2450816933
Short name T283
Test name
Test status
Simulation time 5320500280 ps
CPU time 5.11 seconds
Started Aug 06 04:43:28 PM PDT 24
Finished Aug 06 04:43:34 PM PDT 24
Peak memory 213836 kb
Host smart-cd3fee46-0da1-4baa-93bd-a58a91fc202a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450816933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2450816933
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.663389200
Short name T231
Test name
Test status
Simulation time 5248077616 ps
CPU time 5.06 seconds
Started Aug 06 04:43:20 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 213668 kb
Host smart-5966a62e-2f6e-4aa8-a358-502b6f3b08e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663389200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.663389200
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.4114434434
Short name T24
Test name
Test status
Simulation time 43829611 ps
CPU time 0.7 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:32 PM PDT 24
Peak memory 205228 kb
Host smart-a1498155-7adf-4a00-a0e8-afb307f4a521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114434434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.4114434434
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.602888467
Short name T67
Test name
Test status
Simulation time 7326031459 ps
CPU time 6.88 seconds
Started Aug 06 04:43:22 PM PDT 24
Finished Aug 06 04:43:29 PM PDT 24
Peak memory 205608 kb
Host smart-8e2cb332-1dae-4b39-af32-6d35b8e4eca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602888467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.602888467
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.522084688
Short name T265
Test name
Test status
Simulation time 16171727959 ps
CPU time 19 seconds
Started Aug 06 04:43:29 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 213860 kb
Host smart-6e00bb4f-f304-4b4b-8897-3df66dac95e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522084688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.522084688
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3155585028
Short name T69
Test name
Test status
Simulation time 1150956847 ps
CPU time 2.65 seconds
Started Aug 06 04:43:22 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 213800 kb
Host smart-1c31a213-7b41-4c04-89d8-52e0bb2eea94
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155585028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3155585028
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1234323869
Short name T290
Test name
Test status
Simulation time 1351538353 ps
CPU time 2.84 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:35 PM PDT 24
Peak memory 205564 kb
Host smart-ef104559-2d99-489e-8095-96510199c711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234323869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1234323869
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.663714140
Short name T298
Test name
Test status
Simulation time 4213237347 ps
CPU time 4.08 seconds
Started Aug 06 04:43:19 PM PDT 24
Finished Aug 06 04:43:23 PM PDT 24
Peak memory 213640 kb
Host smart-333db188-85c3-4fd0-b3e6-5196ba4dc981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663714140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.663714140
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2679575166
Short name T226
Test name
Test status
Simulation time 44307714 ps
CPU time 0.73 seconds
Started Aug 06 04:43:40 PM PDT 24
Finished Aug 06 04:43:41 PM PDT 24
Peak memory 205248 kb
Host smart-8d165300-6b9f-49a4-b651-fb4823c102df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679575166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2679575166
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.4041814111
Short name T133
Test name
Test status
Simulation time 8253624987 ps
CPU time 7.95 seconds
Started Aug 06 04:43:27 PM PDT 24
Finished Aug 06 04:43:35 PM PDT 24
Peak memory 213704 kb
Host smart-7aba9a05-0958-4c58-90c4-f0434812eed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041814111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.4041814111
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3398256490
Short name T220
Test name
Test status
Simulation time 3126447331 ps
CPU time 2.44 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:43:56 PM PDT 24
Peak memory 213876 kb
Host smart-67c23477-9727-4191-96a9-3c6849d14435
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398256490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3398256490
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.603741615
Short name T193
Test name
Test status
Simulation time 2240999330 ps
CPU time 3.89 seconds
Started Aug 06 04:43:22 PM PDT 24
Finished Aug 06 04:43:26 PM PDT 24
Peak memory 205644 kb
Host smart-8d62ac8a-f0f2-472a-a86f-cb0d144eec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603741615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.603741615
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.81433935
Short name T229
Test name
Test status
Simulation time 5593509903 ps
CPU time 4.46 seconds
Started Aug 06 04:43:15 PM PDT 24
Finished Aug 06 04:43:19 PM PDT 24
Peak memory 213648 kb
Host smart-051fcaed-1662-46c4-91c6-75d75e8f864a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81433935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.81433935
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4068948500
Short name T167
Test name
Test status
Simulation time 111502458 ps
CPU time 0.74 seconds
Started Aug 06 04:43:30 PM PDT 24
Finished Aug 06 04:43:31 PM PDT 24
Peak memory 205156 kb
Host smart-1393bf79-06fb-4f71-a846-f7faecc44e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068948500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4068948500
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1739881860
Short name T203
Test name
Test status
Simulation time 3867446155 ps
CPU time 11.82 seconds
Started Aug 06 04:43:24 PM PDT 24
Finished Aug 06 04:43:36 PM PDT 24
Peak memory 214892 kb
Host smart-111b9819-ac2d-4e50-8ff0-ee00be48380a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739881860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1739881860
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2833380138
Short name T200
Test name
Test status
Simulation time 2291485332 ps
CPU time 3.86 seconds
Started Aug 06 04:43:19 PM PDT 24
Finished Aug 06 04:43:23 PM PDT 24
Peak memory 213808 kb
Host smart-897e90fb-59eb-435f-abfc-2ab8be54dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833380138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2833380138
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3400322438
Short name T180
Test name
Test status
Simulation time 6142173209 ps
CPU time 9.04 seconds
Started Aug 06 04:43:26 PM PDT 24
Finished Aug 06 04:43:35 PM PDT 24
Peak memory 205664 kb
Host smart-1a8edcdf-6975-4258-87ed-62e3d3416005
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400322438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3400322438
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3857988109
Short name T214
Test name
Test status
Simulation time 12357305153 ps
CPU time 37.86 seconds
Started Aug 06 04:43:39 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 213888 kb
Host smart-46dec2ff-6dd9-4fb7-839b-1e5cc1fe9567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857988109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3857988109
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.3763395391
Short name T140
Test name
Test status
Simulation time 4496894103 ps
CPU time 4.62 seconds
Started Aug 06 04:43:25 PM PDT 24
Finished Aug 06 04:43:30 PM PDT 24
Peak memory 213692 kb
Host smart-328c9a52-56a9-4388-894a-edb14f301112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763395391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3763395391
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1343618124
Short name T281
Test name
Test status
Simulation time 59280871 ps
CPU time 0.76 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:33 PM PDT 24
Peak memory 205168 kb
Host smart-ea13d961-3fe9-4586-b9e5-1a8004ca514d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343618124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1343618124
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3371943943
Short name T247
Test name
Test status
Simulation time 1771369966 ps
CPU time 5.34 seconds
Started Aug 06 04:43:31 PM PDT 24
Finished Aug 06 04:43:36 PM PDT 24
Peak memory 205540 kb
Host smart-dba85222-c6a8-406d-92d9-a2f35c8b0c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371943943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3371943943
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2061058984
Short name T219
Test name
Test status
Simulation time 931841573 ps
CPU time 2.72 seconds
Started Aug 06 04:43:35 PM PDT 24
Finished Aug 06 04:43:37 PM PDT 24
Peak memory 205608 kb
Host smart-c064ae0e-cc14-4df9-9d79-1129cbc3f390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061058984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2061058984
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.853349252
Short name T207
Test name
Test status
Simulation time 6150872135 ps
CPU time 5.94 seconds
Started Aug 06 04:43:23 PM PDT 24
Finished Aug 06 04:43:29 PM PDT 24
Peak memory 205632 kb
Host smart-5ed45ba9-9d80-4eb5-82e9-02a671e38402
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853349252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.853349252
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2579212291
Short name T50
Test name
Test status
Simulation time 632495402 ps
CPU time 2.14 seconds
Started Aug 06 04:43:33 PM PDT 24
Finished Aug 06 04:43:35 PM PDT 24
Peak memory 205572 kb
Host smart-6ca49777-3748-421c-b47b-eda73e549d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579212291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2579212291
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.961114577
Short name T142
Test name
Test status
Simulation time 9812563738 ps
CPU time 9.84 seconds
Started Aug 06 04:43:17 PM PDT 24
Finished Aug 06 04:43:27 PM PDT 24
Peak memory 205408 kb
Host smart-3f14c22b-fe5e-48a1-af46-f7f207b14127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961114577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.961114577
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2604162928
Short name T245
Test name
Test status
Simulation time 61653996 ps
CPU time 0.73 seconds
Started Aug 06 04:43:48 PM PDT 24
Finished Aug 06 04:43:49 PM PDT 24
Peak memory 205160 kb
Host smart-78d34f13-645a-40f6-9d9e-0835e5ddc5e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604162928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2604162928
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.867108575
Short name T221
Test name
Test status
Simulation time 27540925524 ps
CPU time 16.04 seconds
Started Aug 06 04:43:23 PM PDT 24
Finished Aug 06 04:43:39 PM PDT 24
Peak memory 218560 kb
Host smart-c3ae9412-33a2-4211-bca5-3b3070c179c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867108575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.867108575
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.661374918
Short name T168
Test name
Test status
Simulation time 1694980908 ps
CPU time 3.45 seconds
Started Aug 06 04:43:27 PM PDT 24
Finished Aug 06 04:43:31 PM PDT 24
Peak memory 213624 kb
Host smart-c0d9baaa-c897-454a-ad0d-ead08096013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661374918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.661374918
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3254793318
Short name T279
Test name
Test status
Simulation time 1028789445 ps
CPU time 2.07 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:43:39 PM PDT 24
Peak memory 205572 kb
Host smart-20059560-faed-4156-adc9-2600720e4834
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254793318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3254793318
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3931679796
Short name T228
Test name
Test status
Simulation time 2160328131 ps
CPU time 6.82 seconds
Started Aug 06 04:43:24 PM PDT 24
Finished Aug 06 04:43:31 PM PDT 24
Peak memory 205712 kb
Host smart-46cc88c9-1e16-4df7-852f-1d9b64bef5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931679796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3931679796
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3068184750
Short name T128
Test name
Test status
Simulation time 2632217203 ps
CPU time 7.96 seconds
Started Aug 06 04:43:29 PM PDT 24
Finished Aug 06 04:43:37 PM PDT 24
Peak memory 219456 kb
Host smart-86fd8f72-ec68-4787-baa6-a36999379d08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068184750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3068184750
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.722143148
Short name T250
Test name
Test status
Simulation time 61714246 ps
CPU time 0.78 seconds
Started Aug 06 04:43:09 PM PDT 24
Finished Aug 06 04:43:10 PM PDT 24
Peak memory 205144 kb
Host smart-b8c5e0da-d5de-4cc3-a82e-97271ed56f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722143148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.722143148
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1940627565
Short name T66
Test name
Test status
Simulation time 5378440493 ps
CPU time 5.65 seconds
Started Aug 06 04:43:09 PM PDT 24
Finished Aug 06 04:43:15 PM PDT 24
Peak memory 213840 kb
Host smart-27f79ca5-b768-4df6-820e-57911e1059df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940627565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1940627565
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2683150936
Short name T191
Test name
Test status
Simulation time 9228202048 ps
CPU time 25.03 seconds
Started Aug 06 04:43:13 PM PDT 24
Finished Aug 06 04:43:38 PM PDT 24
Peak memory 213820 kb
Host smart-1e65c59a-fe14-4c8d-8781-fe0d1e2cfc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683150936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2683150936
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1577500738
Short name T70
Test name
Test status
Simulation time 1034723048 ps
CPU time 1.11 seconds
Started Aug 06 04:43:09 PM PDT 24
Finished Aug 06 04:43:10 PM PDT 24
Peak memory 205600 kb
Host smart-4cd54e51-e3dc-482e-9f85-89b95f1b6a06
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577500738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1577500738
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.1944740768
Short name T242
Test name
Test status
Simulation time 259997018 ps
CPU time 1.09 seconds
Started Aug 06 04:43:17 PM PDT 24
Finished Aug 06 04:43:19 PM PDT 24
Peak memory 205088 kb
Host smart-cd04a174-480b-4e5b-ad14-966cc556c1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944740768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1944740768
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.671891231
Short name T263
Test name
Test status
Simulation time 234709129 ps
CPU time 1.31 seconds
Started Aug 06 04:43:09 PM PDT 24
Finished Aug 06 04:43:10 PM PDT 24
Peak memory 205156 kb
Host smart-39c69718-9adf-454d-bc2e-ade89f8d3a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671891231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.671891231
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2427219538
Short name T176
Test name
Test status
Simulation time 1651689665 ps
CPU time 1.22 seconds
Started Aug 06 04:43:12 PM PDT 24
Finished Aug 06 04:43:13 PM PDT 24
Peak memory 205508 kb
Host smart-80a447d2-8a8a-46cd-a53f-0c27fd16a44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427219538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2427219538
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.4260444574
Short name T43
Test name
Test status
Simulation time 2696114373 ps
CPU time 7.63 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:19 PM PDT 24
Peak memory 229924 kb
Host smart-598630be-4353-4deb-be08-023fada4e786
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260444574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.4260444574
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.4229422291
Short name T1
Test name
Test status
Simulation time 7199347224 ps
CPU time 11.05 seconds
Started Aug 06 04:43:12 PM PDT 24
Finished Aug 06 04:43:23 PM PDT 24
Peak memory 213608 kb
Host smart-498ec0d3-1072-414c-b9ff-34698739c741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229422291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4229422291
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3960707711
Short name T222
Test name
Test status
Simulation time 82137263 ps
CPU time 0.76 seconds
Started Aug 06 04:43:19 PM PDT 24
Finished Aug 06 04:43:20 PM PDT 24
Peak memory 205132 kb
Host smart-f7fc43a2-bd27-43b0-b153-a4032e29e0ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960707711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3960707711
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2599410902
Short name T13
Test name
Test status
Simulation time 4473711396 ps
CPU time 13.77 seconds
Started Aug 06 04:43:30 PM PDT 24
Finished Aug 06 04:43:44 PM PDT 24
Peak memory 213532 kb
Host smart-ba094a4a-8741-4c03-b5f3-12d60dec229c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599410902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2599410902
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2080403193
Short name T301
Test name
Test status
Simulation time 118306433 ps
CPU time 0.96 seconds
Started Aug 06 04:43:34 PM PDT 24
Finished Aug 06 04:43:35 PM PDT 24
Peak memory 205136 kb
Host smart-d94f92e1-d045-4283-b657-1e77a614f523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080403193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2080403193
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.184105669
Short name T4
Test name
Test status
Simulation time 4513102718 ps
CPU time 6.83 seconds
Started Aug 06 04:43:30 PM PDT 24
Finished Aug 06 04:43:37 PM PDT 24
Peak memory 213740 kb
Host smart-b216f2e0-e692-47d2-97a3-7ea8419eb6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184105669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.184105669
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1882821076
Short name T234
Test name
Test status
Simulation time 54251953 ps
CPU time 0.72 seconds
Started Aug 06 04:43:26 PM PDT 24
Finished Aug 06 04:43:26 PM PDT 24
Peak memory 205132 kb
Host smart-1b14cc15-f01a-4235-870b-533e46d49418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882821076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1882821076
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3869810110
Short name T288
Test name
Test status
Simulation time 2831728622 ps
CPU time 5.05 seconds
Started Aug 06 04:43:36 PM PDT 24
Finished Aug 06 04:43:41 PM PDT 24
Peak memory 213660 kb
Host smart-ec78f4f1-2a98-40a9-a21a-e63721854919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869810110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3869810110
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.785266523
Short name T41
Test name
Test status
Simulation time 89692914 ps
CPU time 0.89 seconds
Started Aug 06 04:43:22 PM PDT 24
Finished Aug 06 04:43:28 PM PDT 24
Peak memory 205124 kb
Host smart-dcae1dbf-1bd2-4557-944b-09ab57bfd4c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785266523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.785266523
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1225041217
Short name T215
Test name
Test status
Simulation time 4080899647 ps
CPU time 5.95 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:43:44 PM PDT 24
Peak memory 213608 kb
Host smart-712d25e8-1fd4-43f5-8572-21813f7b4218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225041217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1225041217
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1180823442
Short name T213
Test name
Test status
Simulation time 60050523 ps
CPU time 0.73 seconds
Started Aug 06 04:43:25 PM PDT 24
Finished Aug 06 04:43:26 PM PDT 24
Peak memory 205208 kb
Host smart-b197d3ee-0a06-4148-bacd-752912c7fff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180823442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1180823442
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.185926069
Short name T243
Test name
Test status
Simulation time 34145239 ps
CPU time 0.75 seconds
Started Aug 06 04:43:28 PM PDT 24
Finished Aug 06 04:43:28 PM PDT 24
Peak memory 205048 kb
Host smart-162d08e4-1a84-4a86-bc3c-0c8b3ffa3de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185926069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.185926069
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.3485247121
Short name T30
Test name
Test status
Simulation time 2547551050 ps
CPU time 4.11 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:36 PM PDT 24
Peak memory 205448 kb
Host smart-ec6d5d9e-c7a7-4ee9-b669-e9fe7831287f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485247121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3485247121
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2192874773
Short name T241
Test name
Test status
Simulation time 62756523 ps
CPU time 0.73 seconds
Started Aug 06 04:43:53 PM PDT 24
Finished Aug 06 04:43:53 PM PDT 24
Peak memory 205132 kb
Host smart-1f5c9d1b-34ad-4a81-a143-81b0a40c58cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192874773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2192874773
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1262973562
Short name T206
Test name
Test status
Simulation time 3006855873 ps
CPU time 8.99 seconds
Started Aug 06 04:43:29 PM PDT 24
Finished Aug 06 04:43:38 PM PDT 24
Peak memory 213712 kb
Host smart-06c1af81-28d5-444e-b3ae-6a405e459b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262973562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1262973562
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3541825158
Short name T218
Test name
Test status
Simulation time 61892213 ps
CPU time 0.82 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:43:39 PM PDT 24
Peak memory 205076 kb
Host smart-adcf6e66-143d-48a2-9604-cf80450b2bd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541825158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3541825158
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.421865521
Short name T146
Test name
Test status
Simulation time 1465616519 ps
CPU time 2.1 seconds
Started Aug 06 04:43:22 PM PDT 24
Finished Aug 06 04:43:24 PM PDT 24
Peak memory 213512 kb
Host smart-86c48b33-7991-4bac-927e-2c12861d6026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421865521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.421865521
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.4264332042
Short name T60
Test name
Test status
Simulation time 38892951 ps
CPU time 0.78 seconds
Started Aug 06 04:43:28 PM PDT 24
Finished Aug 06 04:43:29 PM PDT 24
Peak memory 205176 kb
Host smart-2246577b-4642-4516-b798-66b6e9c64793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264332042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4264332042
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1904256991
Short name T7
Test name
Test status
Simulation time 3753099874 ps
CPU time 3.42 seconds
Started Aug 06 04:43:20 PM PDT 24
Finished Aug 06 04:43:23 PM PDT 24
Peak memory 205324 kb
Host smart-fe986238-5ecb-4260-9cdf-7358c53a90b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904256991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1904256991
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3569073878
Short name T210
Test name
Test status
Simulation time 50438768 ps
CPU time 0.81 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:43:39 PM PDT 24
Peak memory 205068 kb
Host smart-ca7e5437-5e62-4551-aece-65bc99d3902e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569073878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3569073878
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.1893869295
Short name T17
Test name
Test status
Simulation time 3056397651 ps
CPU time 9.27 seconds
Started Aug 06 04:43:39 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 213608 kb
Host smart-b3d77f39-4b84-45b3-9b5f-7354fc7073bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893869295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1893869295
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3843600648
Short name T209
Test name
Test status
Simulation time 149398487 ps
CPU time 0.83 seconds
Started Aug 06 04:43:16 PM PDT 24
Finished Aug 06 04:43:17 PM PDT 24
Peak memory 205180 kb
Host smart-5cd2e4d7-a61f-4939-aa02-e56ddf7a183a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843600648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3843600648
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2227353752
Short name T262
Test name
Test status
Simulation time 2647253191 ps
CPU time 8.14 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:24 PM PDT 24
Peak memory 214848 kb
Host smart-f9239b9d-f586-4d38-99ab-20003d61314b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227353752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2227353752
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3778037196
Short name T238
Test name
Test status
Simulation time 2282848474 ps
CPU time 5.65 seconds
Started Aug 06 04:43:09 PM PDT 24
Finished Aug 06 04:43:14 PM PDT 24
Peak memory 222036 kb
Host smart-772c0a6c-1c38-40d2-968c-c3337adc09ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778037196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3778037196
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.995510378
Short name T188
Test name
Test status
Simulation time 2270040764 ps
CPU time 4.91 seconds
Started Aug 06 04:43:14 PM PDT 24
Finished Aug 06 04:43:19 PM PDT 24
Peak memory 205724 kb
Host smart-6beafc98-0857-4432-9a55-1c65711d81c9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995510378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.995510378
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.285563385
Short name T111
Test name
Test status
Simulation time 959532210 ps
CPU time 3.44 seconds
Started Aug 06 04:43:21 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 205164 kb
Host smart-dc8a1eda-319e-43e2-a612-cc1acafc144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285563385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.285563385
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.8012035
Short name T198
Test name
Test status
Simulation time 459941291 ps
CPU time 1.33 seconds
Started Aug 06 04:43:12 PM PDT 24
Finished Aug 06 04:43:13 PM PDT 24
Peak memory 205140 kb
Host smart-2a73c657-7346-4f0a-a1d4-a41b193c4fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8012035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.8012035
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1779808904
Short name T177
Test name
Test status
Simulation time 1662163876 ps
CPU time 3.17 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:14 PM PDT 24
Peak memory 213696 kb
Host smart-d643cfc9-2be8-4f99-bace-3d64e279b38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779808904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1779808904
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1488318368
Short name T185
Test name
Test status
Simulation time 43530384 ps
CPU time 0.74 seconds
Started Aug 06 04:43:24 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 205140 kb
Host smart-0dc95eee-b3c7-4ab7-860a-05ead5d6a674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488318368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1488318368
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.970908648
Short name T138
Test name
Test status
Simulation time 4476798830 ps
CPU time 2.13 seconds
Started Aug 06 04:43:19 PM PDT 24
Finished Aug 06 04:43:22 PM PDT 24
Peak memory 205444 kb
Host smart-9451b861-a0ba-4773-87d0-8a0edc1f1270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970908648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.970908648
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2030958035
Short name T184
Test name
Test status
Simulation time 140491354 ps
CPU time 0.8 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:43:39 PM PDT 24
Peak memory 205132 kb
Host smart-24c9b7b9-64ee-479c-9ae1-a393693fea92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030958035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2030958035
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.4086691462
Short name T132
Test name
Test status
Simulation time 5184122086 ps
CPU time 4.79 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:37 PM PDT 24
Peak memory 213700 kb
Host smart-1aa0740b-4630-4c09-88bf-1fb0cd2696fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086691462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.4086691462
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1750769860
Short name T174
Test name
Test status
Simulation time 80057040 ps
CPU time 0.67 seconds
Started Aug 06 04:43:24 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 205128 kb
Host smart-3b28a0d5-16d4-42de-ba0d-010ae1795877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750769860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1750769860
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.1620909674
Short name T289
Test name
Test status
Simulation time 1530942219 ps
CPU time 5.55 seconds
Started Aug 06 04:43:43 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 213504 kb
Host smart-a8c479d8-5117-41ca-aab7-5d6431083f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620909674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1620909674
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.737841011
Short name T227
Test name
Test status
Simulation time 71412276 ps
CPU time 0.94 seconds
Started Aug 06 04:43:28 PM PDT 24
Finished Aug 06 04:43:29 PM PDT 24
Peak memory 205072 kb
Host smart-8fbe8a73-e30f-4d8f-bf74-d3c20a6eed6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737841011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.737841011
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.4212395579
Short name T21
Test name
Test status
Simulation time 6704356584 ps
CPU time 4.7 seconds
Started Aug 06 04:43:40 PM PDT 24
Finished Aug 06 04:43:44 PM PDT 24
Peak memory 213668 kb
Host smart-51ee544a-a36d-472a-a861-8af242b5875d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212395579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.4212395579
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.4208697351
Short name T240
Test name
Test status
Simulation time 86135211 ps
CPU time 0.72 seconds
Started Aug 06 04:43:26 PM PDT 24
Finished Aug 06 04:43:27 PM PDT 24
Peak memory 205180 kb
Host smart-fe5d4a87-3539-46e2-8398-f1fac0780c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208697351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.4208697351
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.469693212
Short name T137
Test name
Test status
Simulation time 1832425219 ps
CPU time 4.05 seconds
Started Aug 06 04:43:35 PM PDT 24
Finished Aug 06 04:43:39 PM PDT 24
Peak memory 213512 kb
Host smart-c50fb765-e836-45bd-a0f5-a765bc134af7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469693212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.469693212
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2194922607
Short name T302
Test name
Test status
Simulation time 147809705 ps
CPU time 1.14 seconds
Started Aug 06 04:43:25 PM PDT 24
Finished Aug 06 04:43:27 PM PDT 24
Peak memory 205132 kb
Host smart-4949ceb8-81ec-47bf-8916-71feda1e7c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194922607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2194922607
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2712687572
Short name T8
Test name
Test status
Simulation time 3296561924 ps
CPU time 3.57 seconds
Started Aug 06 04:43:17 PM PDT 24
Finished Aug 06 04:43:21 PM PDT 24
Peak memory 213620 kb
Host smart-7cd91488-2e3f-456a-a3ee-a31b988d6e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712687572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2712687572
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1561939093
Short name T232
Test name
Test status
Simulation time 141749647 ps
CPU time 0.71 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:43:38 PM PDT 24
Peak memory 205168 kb
Host smart-d57d83dd-143a-4e6e-8f11-15c035b1b8d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561939093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1561939093
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2925010300
Short name T36
Test name
Test status
Simulation time 4307818413 ps
CPU time 7.39 seconds
Started Aug 06 04:43:23 PM PDT 24
Finished Aug 06 04:43:31 PM PDT 24
Peak memory 205424 kb
Host smart-0b87163c-7412-42b7-aeb3-0284099a5f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925010300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2925010300
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2894442354
Short name T116
Test name
Test status
Simulation time 79274511 ps
CPU time 0.79 seconds
Started Aug 06 04:43:28 PM PDT 24
Finished Aug 06 04:43:29 PM PDT 24
Peak memory 205180 kb
Host smart-e4057537-d147-4b3d-acc3-95f6d1f4b186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894442354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2894442354
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.946373112
Short name T293
Test name
Test status
Simulation time 9992840792 ps
CPU time 4.29 seconds
Started Aug 06 04:43:31 PM PDT 24
Finished Aug 06 04:43:35 PM PDT 24
Peak memory 213688 kb
Host smart-dead6a7c-aeb4-43db-a693-b0440d9ea5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946373112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.946373112
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1415524907
Short name T171
Test name
Test status
Simulation time 159087692 ps
CPU time 0.81 seconds
Started Aug 06 04:43:41 PM PDT 24
Finished Aug 06 04:43:42 PM PDT 24
Peak memory 205240 kb
Host smart-c9d92cca-2ad1-4e23-8934-6b5dfeee0829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415524907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1415524907
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.946284389
Short name T274
Test name
Test status
Simulation time 2179597673 ps
CPU time 3.02 seconds
Started Aug 06 04:43:28 PM PDT 24
Finished Aug 06 04:43:31 PM PDT 24
Peak memory 213724 kb
Host smart-8bad40d9-687d-4175-acab-da9ca89d6799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946284389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.946284389
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.4047100351
Short name T276
Test name
Test status
Simulation time 81746771 ps
CPU time 0.74 seconds
Started Aug 06 04:43:45 PM PDT 24
Finished Aug 06 04:43:46 PM PDT 24
Peak memory 205252 kb
Host smart-6090e7dd-f0c2-45e7-9efe-23be705c61d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047100351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.4047100351
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3078258946
Short name T33
Test name
Test status
Simulation time 6715093599 ps
CPU time 10.66 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:43 PM PDT 24
Peak memory 221828 kb
Host smart-7905abd2-85d3-47d0-8e50-2f66570a01db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078258946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3078258946
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3190196029
Short name T54
Test name
Test status
Simulation time 78765493 ps
CPU time 0.81 seconds
Started Aug 06 04:43:08 PM PDT 24
Finished Aug 06 04:43:09 PM PDT 24
Peak memory 205168 kb
Host smart-ab6adf7e-fa84-4fd7-b469-9b0abeaf9747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190196029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3190196029
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.118865908
Short name T170
Test name
Test status
Simulation time 49258466364 ps
CPU time 65.27 seconds
Started Aug 06 04:43:13 PM PDT 24
Finished Aug 06 04:44:18 PM PDT 24
Peak memory 213880 kb
Host smart-776748ed-70fe-4bb0-a003-214e0771d3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118865908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.118865908
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2716587212
Short name T296
Test name
Test status
Simulation time 1469285677 ps
CPU time 3.22 seconds
Started Aug 06 04:43:07 PM PDT 24
Finished Aug 06 04:43:10 PM PDT 24
Peak memory 205436 kb
Host smart-32ea0016-2d85-4628-8b24-8686392f8431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716587212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2716587212
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1404977874
Short name T271
Test name
Test status
Simulation time 6629784756 ps
CPU time 9.27 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:21 PM PDT 24
Peak memory 205608 kb
Host smart-f5b7a452-d128-4e89-bd32-3dcdec154e33
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404977874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1404977874
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.3016726816
Short name T32
Test name
Test status
Simulation time 1168828236 ps
CPU time 1.14 seconds
Started Aug 06 04:43:17 PM PDT 24
Finished Aug 06 04:43:18 PM PDT 24
Peak memory 205152 kb
Host smart-926c9d11-ff15-4a11-8485-a90a5c495875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016726816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3016726816
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2296930603
Short name T230
Test name
Test status
Simulation time 393908838 ps
CPU time 1.79 seconds
Started Aug 06 04:43:05 PM PDT 24
Finished Aug 06 04:43:07 PM PDT 24
Peak memory 205096 kb
Host smart-5bf4bb2f-0767-47b1-9be4-f29d79c93c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296930603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2296930603
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2166893712
Short name T277
Test name
Test status
Simulation time 13826727837 ps
CPU time 29.76 seconds
Started Aug 06 04:43:10 PM PDT 24
Finished Aug 06 04:43:39 PM PDT 24
Peak memory 221956 kb
Host smart-85d79124-d819-461b-8312-98955edb644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166893712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2166893712
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.4208175580
Short name T58
Test name
Test status
Simulation time 2565217297 ps
CPU time 3.27 seconds
Started Aug 06 04:43:13 PM PDT 24
Finished Aug 06 04:43:16 PM PDT 24
Peak memory 229588 kb
Host smart-7f35fcd9-7d04-4589-ac65-ccc4795f9590
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208175580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.4208175580
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.3002671398
Short name T27
Test name
Test status
Simulation time 4686708171 ps
CPU time 8.1 seconds
Started Aug 06 04:43:02 PM PDT 24
Finished Aug 06 04:43:11 PM PDT 24
Peak memory 205448 kb
Host smart-958d5c69-0bf6-4387-8033-bc856c083333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002671398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3002671398
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.2665024059
Short name T74
Test name
Test status
Simulation time 37142314294 ps
CPU time 258.42 seconds
Started Aug 06 04:43:09 PM PDT 24
Finished Aug 06 04:47:28 PM PDT 24
Peak memory 229456 kb
Host smart-e49612c9-6f6b-4712-be75-6b6d7cb3ab6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665024059 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.2665024059
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3863864115
Short name T291
Test name
Test status
Simulation time 55052089 ps
CPU time 0.73 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:43:38 PM PDT 24
Peak memory 205172 kb
Host smart-f2d96d17-7bcf-4bdf-8089-4c4dff8807b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863864115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3863864115
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.139303464
Short name T3
Test name
Test status
Simulation time 1743988439 ps
CPU time 4.79 seconds
Started Aug 06 04:43:31 PM PDT 24
Finished Aug 06 04:43:36 PM PDT 24
Peak memory 205388 kb
Host smart-fac5d335-ab53-44c9-ba51-b8f2e8a7d834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139303464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.139303464
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3135805625
Short name T211
Test name
Test status
Simulation time 78216987 ps
CPU time 0.73 seconds
Started Aug 06 04:43:42 PM PDT 24
Finished Aug 06 04:43:42 PM PDT 24
Peak memory 205148 kb
Host smart-0df28e02-9af2-44e2-89c4-4fd9c584eddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135805625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3135805625
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.2801245533
Short name T144
Test name
Test status
Simulation time 3220480456 ps
CPU time 3.22 seconds
Started Aug 06 04:43:54 PM PDT 24
Finished Aug 06 04:43:57 PM PDT 24
Peak memory 205536 kb
Host smart-b7c356f8-a008-49e0-81a0-965f3bbfa62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801245533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2801245533
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2209835243
Short name T117
Test name
Test status
Simulation time 75655008 ps
CPU time 0.8 seconds
Started Aug 06 04:43:30 PM PDT 24
Finished Aug 06 04:43:31 PM PDT 24
Peak memory 205152 kb
Host smart-f762b5d0-aa99-4c4a-93a2-9ff28f8b0eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209835243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2209835243
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3165608950
Short name T303
Test name
Test status
Simulation time 8963348688 ps
CPU time 2.93 seconds
Started Aug 06 04:43:35 PM PDT 24
Finished Aug 06 04:43:38 PM PDT 24
Peak memory 205476 kb
Host smart-0cb20d05-a7d4-4bde-9045-9b8969b9c4df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165608950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3165608950
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.4024244277
Short name T173
Test name
Test status
Simulation time 153078535 ps
CPU time 0.7 seconds
Started Aug 06 04:43:35 PM PDT 24
Finished Aug 06 04:43:35 PM PDT 24
Peak memory 205100 kb
Host smart-2f16acd0-85e8-4f29-8841-27f5546ddeb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024244277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.4024244277
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.4225746376
Short name T299
Test name
Test status
Simulation time 1385576895 ps
CPU time 3.25 seconds
Started Aug 06 04:43:26 PM PDT 24
Finished Aug 06 04:43:30 PM PDT 24
Peak memory 213468 kb
Host smart-801f31f1-6729-40c8-b68f-71ae2367da67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225746376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.4225746376
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2396647052
Short name T284
Test name
Test status
Simulation time 39872062 ps
CPU time 0.68 seconds
Started Aug 06 04:43:39 PM PDT 24
Finished Aug 06 04:43:40 PM PDT 24
Peak memory 205216 kb
Host smart-1f258e70-4519-459b-99a0-3c69c6cb985d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396647052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2396647052
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.544383254
Short name T256
Test name
Test status
Simulation time 2945844693 ps
CPU time 5.94 seconds
Started Aug 06 04:43:42 PM PDT 24
Finished Aug 06 04:43:48 PM PDT 24
Peak memory 205516 kb
Host smart-54fda382-e7c3-4d4d-acd4-ebc19ffe4f51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544383254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.544383254
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2365449761
Short name T269
Test name
Test status
Simulation time 72008361 ps
CPU time 0.7 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:32 PM PDT 24
Peak memory 205176 kb
Host smart-66ebea98-c0c7-46e3-88b5-f09805dfb3f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365449761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2365449761
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1800573965
Short name T135
Test name
Test status
Simulation time 5964402537 ps
CPU time 3.69 seconds
Started Aug 06 04:43:51 PM PDT 24
Finished Aug 06 04:43:55 PM PDT 24
Peak memory 213744 kb
Host smart-84ae4b07-bd71-47c1-86fc-9abadf04cdf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800573965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1800573965
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2431343665
Short name T40
Test name
Test status
Simulation time 138900459 ps
CPU time 0.87 seconds
Started Aug 06 04:43:38 PM PDT 24
Finished Aug 06 04:43:39 PM PDT 24
Peak memory 205076 kb
Host smart-bdb66887-49c0-4c40-8a1b-26d51baa93fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431343665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2431343665
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2223891693
Short name T141
Test name
Test status
Simulation time 6291826057 ps
CPU time 5.4 seconds
Started Aug 06 04:43:32 PM PDT 24
Finished Aug 06 04:43:38 PM PDT 24
Peak memory 213712 kb
Host smart-f76a7eb2-fc62-4496-b3be-e3bd264a64ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223891693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2223891693
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2220151379
Short name T183
Test name
Test status
Simulation time 99260078 ps
CPU time 0.74 seconds
Started Aug 06 04:43:39 PM PDT 24
Finished Aug 06 04:43:40 PM PDT 24
Peak memory 205132 kb
Host smart-60f7d184-5492-4281-a003-21c190def92e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220151379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2220151379
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.469683028
Short name T197
Test name
Test status
Simulation time 4409509335 ps
CPU time 14.41 seconds
Started Aug 06 04:43:40 PM PDT 24
Finished Aug 06 04:43:55 PM PDT 24
Peak memory 205464 kb
Host smart-6f8d95e4-965f-41f0-ab3d-c5713101a97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469683028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.469683028
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2238347293
Short name T172
Test name
Test status
Simulation time 110313981 ps
CPU time 1 seconds
Started Aug 06 04:43:37 PM PDT 24
Finished Aug 06 04:43:38 PM PDT 24
Peak memory 205148 kb
Host smart-98fbc29c-3946-49ac-b3d8-46ba1e067778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238347293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2238347293
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1768386641
Short name T148
Test name
Test status
Simulation time 6042278088 ps
CPU time 2.91 seconds
Started Aug 06 04:43:35 PM PDT 24
Finished Aug 06 04:43:38 PM PDT 24
Peak memory 213684 kb
Host smart-d8d2f70b-48dd-4b59-b6f6-5dd15bae5414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768386641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1768386641
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2716939802
Short name T195
Test name
Test status
Simulation time 61748704 ps
CPU time 0.79 seconds
Started Aug 06 04:43:28 PM PDT 24
Finished Aug 06 04:43:29 PM PDT 24
Peak memory 205076 kb
Host smart-9db3c48b-eef4-4acf-a6f2-52ee2d0a655b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716939802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2716939802
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.1899316433
Short name T143
Test name
Test status
Simulation time 6162519086 ps
CPU time 18.76 seconds
Started Aug 06 04:43:33 PM PDT 24
Finished Aug 06 04:43:52 PM PDT 24
Peak memory 205444 kb
Host smart-beafbdc2-16c5-46e5-8bed-c7b01a37f479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899316433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1899316433
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1375810578
Short name T175
Test name
Test status
Simulation time 113625110 ps
CPU time 0.93 seconds
Started Aug 06 04:43:24 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 205172 kb
Host smart-ea4ed753-695f-4f9c-9873-6ee776c5e996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375810578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1375810578
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2071267146
Short name T266
Test name
Test status
Simulation time 2917371578 ps
CPU time 3.35 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:14 PM PDT 24
Peak memory 205628 kb
Host smart-3a121535-aecc-4889-8da6-ca9b23afc4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071267146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2071267146
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1962858441
Short name T294
Test name
Test status
Simulation time 3435479660 ps
CPU time 4.01 seconds
Started Aug 06 04:43:13 PM PDT 24
Finished Aug 06 04:43:17 PM PDT 24
Peak memory 205592 kb
Host smart-1d1142fb-8beb-41f7-a83f-8ad927896392
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1962858441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1962858441
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.202032478
Short name T164
Test name
Test status
Simulation time 501957592 ps
CPU time 1.92 seconds
Started Aug 06 04:43:14 PM PDT 24
Finished Aug 06 04:43:16 PM PDT 24
Peak memory 205160 kb
Host smart-5ae70445-cb74-4d49-802d-7dfe61d890c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202032478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.202032478
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2026260506
Short name T192
Test name
Test status
Simulation time 2958404865 ps
CPU time 4.66 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:16 PM PDT 24
Peak memory 205640 kb
Host smart-1b534a92-8949-4a51-bd2f-fc41483f8f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026260506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2026260506
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3190696604
Short name T134
Test name
Test status
Simulation time 4773641155 ps
CPU time 7.39 seconds
Started Aug 06 04:43:12 PM PDT 24
Finished Aug 06 04:43:20 PM PDT 24
Peak memory 205484 kb
Host smart-31371d32-c441-4ca7-9236-bf13c6e8be16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190696604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3190696604
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.4251905449
Short name T72
Test name
Test status
Simulation time 52914205050 ps
CPU time 824.5 seconds
Started Aug 06 04:43:02 PM PDT 24
Finished Aug 06 04:56:47 PM PDT 24
Peak memory 230356 kb
Host smart-f673705c-74f3-424b-a187-0130618ad901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251905449 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.4251905449
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.515808005
Short name T258
Test name
Test status
Simulation time 99315533 ps
CPU time 0.71 seconds
Started Aug 06 04:43:10 PM PDT 24
Finished Aug 06 04:43:11 PM PDT 24
Peak memory 205172 kb
Host smart-6ddb2446-d857-4f3b-9084-c84c7493d97e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515808005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.515808005
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1000827446
Short name T149
Test name
Test status
Simulation time 91709476138 ps
CPU time 255 seconds
Started Aug 06 04:43:12 PM PDT 24
Finished Aug 06 04:47:27 PM PDT 24
Peak memory 217616 kb
Host smart-301259cf-82ee-454b-8953-dd7e515312f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000827446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1000827446
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2840429207
Short name T235
Test name
Test status
Simulation time 3651979177 ps
CPU time 9.57 seconds
Started Aug 06 04:43:17 PM PDT 24
Finished Aug 06 04:43:27 PM PDT 24
Peak memory 213848 kb
Host smart-9227c1bc-488d-40d0-af69-d7ac36a5cb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840429207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2840429207
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1537890887
Short name T273
Test name
Test status
Simulation time 2130877938 ps
CPU time 2.04 seconds
Started Aug 06 04:43:14 PM PDT 24
Finished Aug 06 04:43:16 PM PDT 24
Peak memory 214016 kb
Host smart-6d0a6adc-f46e-4176-b26f-3e9eb5d64d01
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1537890887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1537890887
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.3815498095
Short name T59
Test name
Test status
Simulation time 1102982437 ps
CPU time 3.96 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:15 PM PDT 24
Peak memory 205208 kb
Host smart-6e27ea13-f7b1-4cb5-9ac7-c603285c1287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815498095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3815498095
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2084170071
Short name T169
Test name
Test status
Simulation time 6468525851 ps
CPU time 11.01 seconds
Started Aug 06 04:43:14 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 205712 kb
Host smart-c4380b26-b8f1-4a52-bf06-4807e169443b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084170071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2084170071
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2169017833
Short name T253
Test name
Test status
Simulation time 2679466305 ps
CPU time 3.37 seconds
Started Aug 06 04:43:17 PM PDT 24
Finished Aug 06 04:43:21 PM PDT 24
Peak memory 213636 kb
Host smart-33106876-983b-4e44-8a20-090fc506dfc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169017833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2169017833
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2847416563
Short name T120
Test name
Test status
Simulation time 76644566 ps
CPU time 0.89 seconds
Started Aug 06 04:43:17 PM PDT 24
Finished Aug 06 04:43:18 PM PDT 24
Peak memory 205144 kb
Host smart-5731be15-a3dc-44e6-a07c-a750e216fac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847416563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2847416563
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.371622308
Short name T64
Test name
Test status
Simulation time 15809044025 ps
CPU time 46.12 seconds
Started Aug 06 04:43:15 PM PDT 24
Finished Aug 06 04:44:01 PM PDT 24
Peak memory 213888 kb
Host smart-305a05a1-deff-492e-a703-0ade71cd14b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371622308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.371622308
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.931421385
Short name T285
Test name
Test status
Simulation time 1224950499 ps
CPU time 1.89 seconds
Started Aug 06 04:43:13 PM PDT 24
Finished Aug 06 04:43:15 PM PDT 24
Peak memory 214100 kb
Host smart-ad069934-a69f-48ec-8a05-022d6bd93751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931421385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.931421385
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1158801695
Short name T196
Test name
Test status
Simulation time 2571406653 ps
CPU time 7.37 seconds
Started Aug 06 04:43:02 PM PDT 24
Finished Aug 06 04:43:09 PM PDT 24
Peak memory 205584 kb
Host smart-e20c63e3-a401-44fd-bb6c-854222febcd8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158801695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1158801695
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.1007681133
Short name T278
Test name
Test status
Simulation time 224255611 ps
CPU time 1.22 seconds
Started Aug 06 04:43:09 PM PDT 24
Finished Aug 06 04:43:10 PM PDT 24
Peak memory 205112 kb
Host smart-dfa4a8a8-0c5d-4e15-b517-1a7f7fcbde3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007681133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.1007681133
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1460431906
Short name T182
Test name
Test status
Simulation time 5219760723 ps
CPU time 4.11 seconds
Started Aug 06 04:43:19 PM PDT 24
Finished Aug 06 04:43:24 PM PDT 24
Peak memory 205572 kb
Host smart-022800af-eafc-40d0-9a8a-ed3b07c7fd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460431906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1460431906
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1448270064
Short name T233
Test name
Test status
Simulation time 7343331769 ps
CPU time 12.96 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:24 PM PDT 24
Peak memory 213720 kb
Host smart-40ade076-aee8-4511-8ab2-1917ab4a779a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448270064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1448270064
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.910192093
Short name T119
Test name
Test status
Simulation time 143251829 ps
CPU time 0.77 seconds
Started Aug 06 04:43:33 PM PDT 24
Finished Aug 06 04:43:34 PM PDT 24
Peak memory 205116 kb
Host smart-e0b6f182-651b-4cf6-8be6-34ccdc5657fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910192093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.910192093
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1454077012
Short name T264
Test name
Test status
Simulation time 1334828100 ps
CPU time 4.81 seconds
Started Aug 06 04:43:21 PM PDT 24
Finished Aug 06 04:43:26 PM PDT 24
Peak memory 213716 kb
Host smart-a6e00ebc-e802-4a70-8cf0-61bf6ebd3314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454077012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1454077012
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.816628583
Short name T65
Test name
Test status
Simulation time 5940508990 ps
CPU time 9.79 seconds
Started Aug 06 04:43:29 PM PDT 24
Finished Aug 06 04:43:39 PM PDT 24
Peak memory 213816 kb
Host smart-a9774a80-6e57-4cfd-8e31-8517a8ebda23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816628583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.816628583
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3370350435
Short name T199
Test name
Test status
Simulation time 5703438611 ps
CPU time 16.44 seconds
Started Aug 06 04:43:18 PM PDT 24
Finished Aug 06 04:43:35 PM PDT 24
Peak memory 213812 kb
Host smart-ad5f4753-11e1-4346-af8e-7eaccad54737
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370350435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3370350435
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.575846674
Short name T295
Test name
Test status
Simulation time 7273520724 ps
CPU time 21.23 seconds
Started Aug 06 04:43:11 PM PDT 24
Finished Aug 06 04:43:32 PM PDT 24
Peak memory 214148 kb
Host smart-7b152ad9-6b8f-4be6-a284-17d5c0eb780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575846674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.575846674
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.1344799768
Short name T150
Test name
Test status
Simulation time 9727082162 ps
CPU time 2.89 seconds
Started Aug 06 04:43:21 PM PDT 24
Finished Aug 06 04:43:24 PM PDT 24
Peak memory 205424 kb
Host smart-969d2e73-001e-4977-9ae9-3b7846221c93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344799768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.1344799768
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.1168144882
Short name T35
Test name
Test status
Simulation time 366401269696 ps
CPU time 993.23 seconds
Started Aug 06 04:43:44 PM PDT 24
Finished Aug 06 05:00:18 PM PDT 24
Peak memory 236536 kb
Host smart-6f0a96ea-f7b3-4fcf-a18f-105f8031a7f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168144882 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.1168144882
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3475513993
Short name T286
Test name
Test status
Simulation time 135101976 ps
CPU time 0.94 seconds
Started Aug 06 04:43:24 PM PDT 24
Finished Aug 06 04:43:25 PM PDT 24
Peak memory 205220 kb
Host smart-22aa140a-c7ee-4641-9131-3bbf83db62a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475513993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3475513993
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.170473846
Short name T20
Test name
Test status
Simulation time 14571377544 ps
CPU time 41.69 seconds
Started Aug 06 04:43:26 PM PDT 24
Finished Aug 06 04:44:08 PM PDT 24
Peak memory 213796 kb
Host smart-a06a3553-c14a-4dcc-8b97-b8f97da178fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170473846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.170473846
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2497740447
Short name T186
Test name
Test status
Simulation time 1240548247 ps
CPU time 4.35 seconds
Started Aug 06 04:43:28 PM PDT 24
Finished Aug 06 04:43:33 PM PDT 24
Peak memory 221828 kb
Host smart-4fc1e4b8-1355-447a-895c-aa6ea0ea63fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497740447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2497740447
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1720408738
Short name T12
Test name
Test status
Simulation time 3924007531 ps
CPU time 12.26 seconds
Started Aug 06 04:43:26 PM PDT 24
Finished Aug 06 04:43:43 PM PDT 24
Peak memory 213804 kb
Host smart-f450107e-ec30-49d1-8b57-5d1a7aad44ac
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720408738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1720408738
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1943531079
Short name T68
Test name
Test status
Simulation time 1675966365 ps
CPU time 3.24 seconds
Started Aug 06 04:43:16 PM PDT 24
Finished Aug 06 04:43:19 PM PDT 24
Peak memory 205596 kb
Host smart-8a4a2f59-b254-4e3f-819c-83de71411bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943531079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1943531079
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.4275812686
Short name T145
Test name
Test status
Simulation time 5341715776 ps
CPU time 8.6 seconds
Started Aug 06 04:43:46 PM PDT 24
Finished Aug 06 04:43:54 PM PDT 24
Peak memory 213684 kb
Host smart-ca3e9eca-d7da-452a-bb7c-c26705fc5693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275812686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.4275812686
Directory /workspace/9.rv_dm_stress_all/latest
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