Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	725833	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1029580

1

T1

5

T2

3

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	631833	1			T1	4		T2	3		T3	1
values[0x0]	354213	1			T1	6		T2	2		T3	12
values[0x1]	769367	1			T1	4		T2	2		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	348630	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1406783

1

T1

6

T2

3

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7823	1			T1	1		T3	2		T42	1
valid_sources[0x01]	7408	1			T24	441		T8	794		T171	2
valid_sources[0x02]	6262	1			T24	529		T19	2		T8	805
valid_sources[0x03]	6981	1			T24	659		T8	838		T44	262
valid_sources[0x04]	6905	1			T42	1		T24	748		T91	2
valid_sources[0x05]	6281	1			T38	1		T17	1		T24	460
valid_sources[0x06]	7117	1			T24	472		T7	1		T8	820
valid_sources[0x07]	6869	1			T13	1		T24	548		T8	832
valid_sources[0x08]	7128	1			T33	1		T17	2		T24	491
valid_sources[0x09]	6935	1			T24	455		T8	802		T15	1
valid_sources[0x0a]	6787	1			T24	571		T8	784		T44	259
valid_sources[0x0b]	6906	1			T33	1		T43	2		T24	556
valid_sources[0x0c]	7518	1			T144	1		T24	514		T8	864
valid_sources[0x0d]	6833	1			T38	1		T24	516		T8	826
valid_sources[0x0e]	6561	1			T6	1		T24	518		T8	829
valid_sources[0x0f]	6333	1			T38	1		T24	412		T8	818
valid_sources[0x10]	6941	1			T1	1		T5	1		T24	388
valid_sources[0x11]	6811	1			T144	1		T24	433		T145	1
valid_sources[0x12]	7276	1			T24	447		T8	809		T44	270
valid_sources[0x13]	7457	1			T33	1		T24	683		T8	813
valid_sources[0x14]	6492	1			T1	1		T6	1		T24	449
valid_sources[0x15]	6960	1			T38	1		T144	3		T24	365
valid_sources[0x16]	7257	1			T24	611		T8	805		T44	241
valid_sources[0x17]	6845	1			T24	557		T8	788		T44	251
valid_sources[0x18]	6279	1			T43	1		T38	1		T24	502
valid_sources[0x19]	7022	1			T1	1		T3	1		T24	352
valid_sources[0x1a]	7466	1			T6	1		T24	617		T172	3
valid_sources[0x1b]	6611	1			T40	1		T24	445		T8	818
valid_sources[0x1c]	6862	1			T24	370		T8	792		T44	262
valid_sources[0x1d]	7281	1			T43	2		T24	474		T8	774
valid_sources[0x1e]	6524	1			T17	4		T12	4		T24	397
valid_sources[0x1f]	6719	1			T6	1		T24	515		T8	798
valid_sources[0x20]	6355	1			T12	3		T24	382		T8	771
valid_sources[0x21]	6573	1			T3	1		T38	1		T24	365
valid_sources[0x22]	6606	1			T24	342		T8	839		T173	1
valid_sources[0x23]	7037	1			T58	1		T24	569		T8	844
valid_sources[0x24]	6246	1			T33	2		T24	367		T8	781
valid_sources[0x25]	6234	1			T24	425		T8	790		T44	276
valid_sources[0x26]	6885	1			T24	425		T8	792		T44	279
valid_sources[0x27]	7208	1			T6	1		T24	254		T8	822
valid_sources[0x28]	6802	1			T43	1		T24	361		T8	777
valid_sources[0x29]	6829	1			T24	464		T8	837		T44	294
valid_sources[0x2a]	6760	1			T12	1		T24	457		T8	845
valid_sources[0x2b]	6796	1			T17	1		T24	349		T8	805
valid_sources[0x2c]	6427	1			T33	1		T17	3		T24	347
valid_sources[0x2d]	6825	1			T24	488		T8	793		T158	1
valid_sources[0x2e]	6544	1			T33	1		T24	481		T8	768
valid_sources[0x2f]	6468	1			T4	1		T24	453		T159	1
valid_sources[0x30]	6984	1			T4	1		T43	1		T24	357
valid_sources[0x31]	6889	1			T24	379		T19	1		T8	821
valid_sources[0x32]	6926	1			T144	2		T6	2		T24	464
valid_sources[0x33]	6810	1			T24	490		T8	831		T44	282
valid_sources[0x34]	7282	1			T3	1		T24	465		T18	1
valid_sources[0x35]	6921	1			T24	533		T8	797		T44	269
valid_sources[0x36]	6090	1			T24	385		T145	1		T8	831
valid_sources[0x37]	6950	1			T144	2		T46	11		T13	1
valid_sources[0x38]	6600	1			T17	2		T24	410		T8	802
valid_sources[0x39]	6712	1			T58	1		T24	664		T174	1
valid_sources[0x3a]	6919	1			T144	1		T24	564		T175	1
valid_sources[0x3b]	6827	1			T24	526		T176	1		T8	800
valid_sources[0x3c]	6835	1			T1	1		T24	572		T8	761
valid_sources[0x3d]	7039	1			T45	1		T38	1		T144	1
valid_sources[0x3e]	7155	1			T6	2		T24	509		T159	1
valid_sources[0x3f]	6468	1			T43	1		T24	552		T8	760
valid_sources[0x40]	6545	1			T3	1		T24	479		T8	815
valid_sources[0x41]	7638	1			T5	1		T24	426		T52	9
valid_sources[0x42]	6728	1			T33	2		T144	2		T17	2
valid_sources[0x43]	7604	1			T24	520		T18	1		T8	851
valid_sources[0x44]	6659	1			T1	1		T58	1		T43	1
valid_sources[0x45]	6995	1			T6	1		T24	425		T145	1
valid_sources[0x46]	6336	1			T24	424		T8	748		T44	311
valid_sources[0x47]	7253	1			T38	1		T24	275		T8	774
valid_sources[0x48]	5990	1			T28	2		T144	1		T24	372
valid_sources[0x49]	6879	1			T24	495		T172	1		T8	785
valid_sources[0x4a]	6811	1			T33	1		T6	1		T24	335
valid_sources[0x4b]	6291	1			T24	412		T145	1		T8	810
valid_sources[0x4c]	6660	1			T40	6		T17	2		T24	378
valid_sources[0x4d]	6491	1			T24	365		T8	794		T44	284
valid_sources[0x4e]	7387	1			T38	1		T24	409		T19	4
valid_sources[0x4f]	7113	1			T24	523		T8	859		T44	242
valid_sources[0x50]	6732	1			T24	517		T8	822		T44	306
valid_sources[0x51]	7003	1			T24	481		T8	751		T44	258
valid_sources[0x52]	6326	1			T38	1		T24	521		T8	807
valid_sources[0x53]	7114	1			T24	413		T8	804		T44	290
valid_sources[0x54]	7782	1			T33	1		T24	527		T8	746
valid_sources[0x55]	7046	1			T58	3		T45	1		T38	1
valid_sources[0x56]	6731	1			T17	1		T24	351		T176	1
valid_sources[0x57]	6868	1			T144	1		T24	613		T8	755
valid_sources[0x58]	6697	1			T3	1		T177	2		T144	3
valid_sources[0x59]	6806	1			T42	2		T144	1		T6	1
valid_sources[0x5a]	6740	1			T38	2		T13	1		T24	482
valid_sources[0x5b]	6598	1			T38	2		T24	361		T18	2
valid_sources[0x5c]	6640	1			T3	1		T33	1		T24	516
valid_sources[0x5d]	6519	1			T33	1		T13	3		T24	381
valid_sources[0x5e]	6966	1			T22	5		T24	569		T18	1
valid_sources[0x5f]	6775	1			T24	533		T8	770		T44	282
valid_sources[0x60]	6500	1			T4	1		T43	1		T24	491
valid_sources[0x61]	6206	1			T4	1		T24	479		T145	3
valid_sources[0x62]	7152	1			T38	1		T178	4		T24	347
valid_sources[0x63]	6804	1			T24	366		T8	822		T44	265
valid_sources[0x64]	6768	1			T43	1		T24	465		T176	1
valid_sources[0x65]	6549	1			T33	1		T24	440		T159	1
valid_sources[0x66]	6579	1			T4	1		T41	9		T24	459
valid_sources[0x67]	6785	1			T33	1		T6	1		T24	472
valid_sources[0x68]	6393	1			T33	1		T17	1		T24	506
valid_sources[0x69]	6801	1			T3	1		T33	1		T24	340
valid_sources[0x6a]	6797	1			T12	1		T24	617		T8	773
valid_sources[0x6b]	7165	1			T58	1		T16	8		T6	1
valid_sources[0x6c]	6811	1			T1	2		T24	379		T8	799
valid_sources[0x6d]	6372	1			T3	1		T38	1		T13	1
valid_sources[0x6e]	6358	1			T24	450		T174	1		T8	786
valid_sources[0x6f]	7247	1			T42	1		T24	484		T8	841
valid_sources[0x70]	6691	1			T33	1		T43	1		T24	517
valid_sources[0x71]	6324	1			T58	5		T6	1		T24	467
valid_sources[0x72]	6371	1			T1	1		T24	471		T8	845
valid_sources[0x73]	7575	1			T58	2		T38	2		T23	16
valid_sources[0x74]	7532	1			T3	1		T4	1		T6	1
valid_sources[0x75]	8032	1			T24	452		T8	809		T44	301
valid_sources[0x76]	7038	1			T38	1		T24	393		T8	815
valid_sources[0x77]	6703	1			T43	1		T38	1		T24	609
valid_sources[0x78]	6238	1			T24	339		T176	1		T8	717
valid_sources[0x79]	6681	1			T38	2		T24	323		T145	1
valid_sources[0x7a]	6850	1			T1	1		T13	2		T24	330
valid_sources[0x7b]	6822	1			T38	2		T144	2		T24	454
valid_sources[0x7c]	6989	1			T42	2		T24	456		T8	754
valid_sources[0x7d]	6573	1			T4	1		T24	399		T8	840
valid_sources[0x7e]	6906	1			T4	1		T45	1		T24	421
valid_sources[0x7f]	6859	1			T24	539		T8	783		T44	267
valid_sources[0x80]	7108	1			T24	496		T8	794		T47	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

413080

1

T1

2

T2

3

T4

2

values[0x0]

all_enables

biggest_size

307900

1

T3

4

T28

1

T42

1

values[0x1]

all_enables

biggest_size

308600

1

T1

3

T3

4

T4

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

671929

1

T1

8

T2

1

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	182507	1			T24	23394		T8	36376		T44	12654
values[0x0]	254367	1			T1	7		T2	1		T3	3
values[0x1]	267195	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17352	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

686717

1

T1

8

T2

1

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2983	1			T179	1		T24	359		T89	1
valid_sources[0x01]	2129	1			T23	1		T24	374		T89	1
valid_sources[0x02]	2652	1			T180	1		T24	322		T181	1
valid_sources[0x03]	2689	1			T24	346		T89	1		T175	2
valid_sources[0x04]	2511	1			T24	392		T8	594		T44	185
valid_sources[0x05]	2083	1			T24	335		T8	266		T44	162
valid_sources[0x06]	2280	1			T73	1		T24	338		T8	383
valid_sources[0x07]	2665	1			T31	1		T24	379		T8	662
valid_sources[0x08]	2686	1			T23	1		T24	363		T182	1
valid_sources[0x09]	2359	1			T183	1		T24	366		T8	384
valid_sources[0x0a]	2937	1			T24	344		T8	628		T44	195
valid_sources[0x0b]	3279	1			T184	1		T24	346		T89	1
valid_sources[0x0c]	2997	1			T75	1		T185	1		T24	369
valid_sources[0x0d]	3243	1			T24	348		T186	14		T8	944
valid_sources[0x0e]	2250	1			T185	1		T24	368		T71	1
valid_sources[0x0f]	3388	1			T10	1		T24	325		T8	1261
valid_sources[0x10]	2598	1			T24	323		T8	600		T44	189
valid_sources[0x11]	3509	1			T24	366		T85	1		T182	1
valid_sources[0x12]	2132	1			T58	3		T73	1		T24	364
valid_sources[0x13]	2858	1			T187	1		T24	350		T8	736
valid_sources[0x14]	2808	1			T188	2		T24	353		T147	6
valid_sources[0x15]	1973	1			T153	1		T24	330		T8	39
valid_sources[0x16]	3289	1			T24	358		T189	1		T8	792
valid_sources[0x17]	2340	1			T24	392		T8	331		T44	174
valid_sources[0x18]	3279	1			T144	1		T24	385		T8	729
valid_sources[0x19]	2300	1			T25	1		T190	1		T24	331
valid_sources[0x1a]	3642	1			T191	1		T24	390		T8	1334
valid_sources[0x1b]	2786	1			T24	331		T8	826		T44	186
valid_sources[0x1c]	2766	1			T26	6		T190	1		T24	378
valid_sources[0x1d]	2908	1			T24	365		T8	719		T192	1
valid_sources[0x1e]	2689	1			T24	320		T64	5		T148	5
valid_sources[0x1f]	2604	1			T10	1		T24	385		T8	377
valid_sources[0x20]	2637	1			T24	351		T8	584		T171	1
valid_sources[0x21]	2995	1			T24	373		T8	489		T44	170
valid_sources[0x22]	2253	1			T193	3		T24	371		T89	1
valid_sources[0x23]	2764	1			T193	3		T24	354		T8	326
valid_sources[0x24]	3451	1			T180	3		T24	381		T194	1
valid_sources[0x25]	3062	1			T195	4		T24	342		T8	752
valid_sources[0x26]	3157	1			T196	1		T24	342		T89	1
valid_sources[0x27]	2768	1			T190	1		T24	355		T8	661
valid_sources[0x28]	3280	1			T33	1		T73	1		T79	3
valid_sources[0x29]	3155	1			T24	346		T8	780		T44	179
valid_sources[0x2a]	3023	1			T144	1		T24	366		T197	1
valid_sources[0x2b]	3173	1			T24	367		T145	1		T8	231
valid_sources[0x2c]	2658	1			T24	364		T145	1		T8	436
valid_sources[0x2d]	3142	1			T41	1		T24	307		T8	1125
valid_sources[0x2e]	2782	1			T24	380		T86	7		T8	198
valid_sources[0x2f]	2414	1			T11	1		T196	1		T24	360
valid_sources[0x30]	3378	1			T4	1		T5	3		T24	346
valid_sources[0x31]	2244	1			T67	1		T75	1		T24	374
valid_sources[0x32]	2468	1			T24	357		T18	1		T8	476
valid_sources[0x33]	2674	1			T33	1		T24	388		T8	520
valid_sources[0x34]	3848	1			T180	2		T198	1		T24	379
valid_sources[0x35]	3294	1			T24	334		T8	705		T44	226
valid_sources[0x36]	2322	1			T54	9		T24	323		T8	285
valid_sources[0x37]	2520	1			T24	315		T154	1		T8	506
valid_sources[0x38]	3085	1			T24	344		T8	722		T44	197
valid_sources[0x39]	2905	1			T131	1		T187	1		T24	371
valid_sources[0x3a]	2394	1			T24	356		T89	1		T194	1
valid_sources[0x3b]	2850	1			T24	367		T8	918		T44	169
valid_sources[0x3c]	3253	1			T14	1		T199	1		T24	389
valid_sources[0x3d]	2321	1			T200	1		T24	381		T8	257
valid_sources[0x3e]	2735	1			T73	1		T24	339		T145	1
valid_sources[0x3f]	2853	1			T185	1		T24	341		T8	481
valid_sources[0x40]	2620	1			T24	387		T8	442		T44	174
valid_sources[0x41]	3226	1			T201	1		T24	349		T37	1
valid_sources[0x42]	2821	1			T141	2		T188	1		T24	342
valid_sources[0x43]	3330	1			T187	1		T46	1		T13	8
valid_sources[0x44]	2614	1			T24	356		T202	1		T8	743
valid_sources[0x45]	2494	1			T1	2		T203	3		T24	365
valid_sources[0x46]	2345	1			T131	3		T180	1		T24	359
valid_sources[0x47]	2699	1			T24	394		T8	372		T44	172
valid_sources[0x48]	2430	1			T40	2		T24	356		T145	1
valid_sources[0x49]	3381	1			T24	379		T8	526		T157	1
valid_sources[0x4a]	2872	1			T177	1		T24	381		T204	5
valid_sources[0x4b]	3145	1			T187	1		T24	384		T8	354
valid_sources[0x4c]	2930	1			T24	377		T8	593		T44	197
valid_sources[0x4d]	2942	1			T180	1		T24	381		T154	1
valid_sources[0x4e]	2778	1			T24	360		T205	1		T172	8
valid_sources[0x4f]	2554	1			T24	359		T206	1		T8	180
valid_sources[0x50]	2503	1			T187	1		T188	1		T24	358
valid_sources[0x51]	3586	1			T24	333		T202	1		T8	1397
valid_sources[0x52]	2923	1			T196	1		T23	1		T24	322
valid_sources[0x53]	2539	1			T75	1		T24	353		T161	1
valid_sources[0x54]	2400	1			T185	1		T24	374		T202	1
valid_sources[0x55]	2666	1			T23	1		T24	356		T8	505
valid_sources[0x56]	2414	1			T67	1		T24	368		T182	1
valid_sources[0x57]	2172	1			T16	9		T24	346		T8	242
valid_sources[0x58]	2749	1			T196	1		T24	361		T8	756
valid_sources[0x59]	2394	1			T190	1		T24	354		T8	513
valid_sources[0x5a]	3177	1			T31	2		T185	1		T24	356
valid_sources[0x5b]	2724	1			T33	1		T23	1		T24	363
valid_sources[0x5c]	3677	1			T33	1		T24	369		T8	1598
valid_sources[0x5d]	2687	1			T24	384		T90	12		T8	470
valid_sources[0x5e]	2255	1			T75	1		T24	326		T8	487
valid_sources[0x5f]	3117	1			T196	1		T24	367		T8	649
valid_sources[0x60]	2335	1			T201	1		T24	380		T88	1
valid_sources[0x61]	2597	1			T42	1		T180	2		T24	338
valid_sources[0x62]	2491	1			T73	1		T24	354		T8	628
valid_sources[0x63]	2508	1			T4	1		T24	394		T8	378
valid_sources[0x64]	2796	1			T2	1		T24	394		T8	533
valid_sources[0x65]	3146	1			T24	398		T8	744		T44	166
valid_sources[0x66]	2956	1			T190	2		T178	1		T24	361
valid_sources[0x67]	1821	1			T187	1		T24	344		T202	1
valid_sources[0x68]	3056	1			T180	1		T24	387		T20	1
valid_sources[0x69]	4133	1			T4	1		T24	381		T8	1088
valid_sources[0x6a]	2862	1			T24	356		T207	1		T8	417
valid_sources[0x6b]	2659	1			T24	372		T159	1		T71	2
valid_sources[0x6c]	2130	1			T131	2		T180	1		T24	385
valid_sources[0x6d]	2170	1			T24	355		T161	1		T8	320
valid_sources[0x6e]	2382	1			T208	1		T24	386		T71	1
valid_sources[0x6f]	2332	1			T33	1		T23	1		T24	350
valid_sources[0x70]	2153	1			T53	1		T22	1		T24	364
valid_sources[0x71]	3183	1			T24	385		T8	536		T44	207
valid_sources[0x72]	2452	1			T131	1		T144	1		T193	1
valid_sources[0x73]	2734	1			T131	1		T24	349		T8	757
valid_sources[0x74]	2689	1			T209	1		T24	391		T8	190
valid_sources[0x75]	2351	1			T183	1		T24	356		T8	532
valid_sources[0x76]	3344	1			T22	4		T24	336		T8	1010
valid_sources[0x77]	2986	1			T24	365		T8	296		T44	199
valid_sources[0x78]	2355	1			T199	2		T24	357		T8	443
valid_sources[0x79]	2963	1			T73	1		T191	1		T24	383
valid_sources[0x7a]	3125	1			T1	2		T24	305		T8	1001
valid_sources[0x7b]	2688	1			T24	380		T8	350		T157	1
valid_sources[0x7c]	2504	1			T45	1		T24	374		T62	1
valid_sources[0x7d]	2528	1			T24	380		T8	614		T44	176
valid_sources[0x7e]	2541	1			T63	6		T40	1		T31	1
valid_sources[0x7f]	2598	1			T1	1		T24	346		T8	703
valid_sources[0x80]	2554	1			T24	324		T8	615		T44	180

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

169970

1

T24

22155

T8

34404

T44

11984

values[0x0]

all_enables

biggest_size

251539

1

T1

7

T2

1

T3

3

values[0x1]

all_enables

biggest_size

250420

1

T1

1

T3

1

T9

1